Stanford Research Systems SR844, User Manual

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6-18 Circuit Descriptions
SR844 RF Lock-In Amplifier
platform interface section of the motherboard 84MBD. Components R210–212 and
C210 are an input matching network.
Half of U216 (U216A) is used as a very fast buffer. The input network R214–215,
C213–214, Z214–215 provides DC blocking, overvoltage protection to 50V, and current
limiting. The several parallel paths in this network ensure that there is a suitable signal
path at all input frequencies. R217–218 provide a DC path to ground for the buffer
input, and also define the input resistance in the high-impedance case. C215 and R216
are to prevent unwanted oscillations. P216 controls the quiescent current drawn by
U216; the voltage measured across JP216 should be 50.6 mV, but this is not critical.
The buffered signal drives two diode-capacitor pairs through R221. D220 charges C220
to the maximum value of the signal waveform, this value is buffered by follower U220A.
Similarly C221 is charged to the signal minimum, and this voltage is buffered by U220B.
R222 and R223 are bleed resistors that drain charge off C220 and C221 respectively,
enabling the capacitors to track decreases in signal amplitude. N220 is a voltage divider;
the voltage at node N220.2 is filtered by Z220–222 and has a value that is the mean of
the signal maximum and the signal minimum. This voltage is buffered by U230 and is
the threshold voltage used to define the edge, or phase zero point, of the reference input
waveform. Remember that U216A is AC coupled, so the extrema and threshold may not
be the same voltages as are on the raw input signal.
The other half of U216 (U216B) is an operational transconductance amplifier (OTA) that
operates as a difference amplifier. The voltage at U216.8 is proportional to the
difference between the buffered signal on U216.3 and the threshold on U216.2. The
components R233, Z231, L230 and Z230 constitute a reverse filter that prevents high-
frequency signals from going back from U216 to U230.
U234 is an ECL comparator set to a threshold of nominally zero volts. Note that the zero
threshold is the same point on the waveform at which the signal is equal to its threshold
value (mean of the signal extrema). R240 and N234 provide 30mV hysteresis, with
C234 providing a fast boost to the hysteresis. P234 is provided to null any accumulated
offsets in the threshold level; it is adjusted so that a sine-wave input gives an output
waveform with 50% duty cycle.
The outputs of U234 go to the phase comparator.
XPHSC: Phase Comparator
The inputs to the phase comparator are ECL square waves at the reference frequency,
one
Q/-Q
pair from U234 above, and the other from the divider chain on 84DVC. These
signals are buffered by U300 and U302, the outputs being correctly referenced to local
ground. U304 is the phase comparator, the
U
and
-U
lines go active when the U304.6
lags U304.7, while the
D/-D
lines go active when U304.6 leads U304.7. One pair of
outputs,
-U/-D
, go to the loop filter below, while the other pair is used for sensing
unlock.
U310 is configured as a differential amplifier with
×
10 gain. The idea is that when the
circuit is phase-locked, both
U
and
D
are at ECL low and the diff amp output U310.6 is
nominally zero. When unlocked, any activity on
U
or
D
causes U310.6 to deviate from