Stanford Research Systems SR844, User Manual

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Circuit Descriptions 6-21
SR844 RF Lock-In Amplifier
DVCR: Multiplexer Control Bits
Appropriate taps are taken from the divider chain depending on the range (octave) within
which the reference frequency lies, and also depending on whether the instrument is in
2nd harmonic mode or not. The multiplexer control bits are derived from the 5 inputs :
RANGE0
–
RANGE3
and
MODE2F
, all of which come from the motherboard 84MBD.
The control bits are generated using gates U642 and programmable logic chips U640,
U651. TTL bits are buffered with 1.0K resistors for isolation, while bits for ECL
multiplexers are converted from TTL to ECL levels using resistor networks such as
N660 and N661. The nomenclature for the control bits is as follows, letter S is used for
ECL bits and T for TTL bits, the first number (25 in
S25S0
, for example) denotes which
chip the control bit goes to (25 means U625) and the trailing number (0 in the example)
denotes which control bit, 0 being the LSB, 2 the MSB, and 3 is the gate/enable on chips
that require it.
T44T3
is a TTL control bit going to the gate of U644.
The range bits are defined as shown in the following table: note that
RANGE0
is the Most
Significant Bit (MSB). The frequencies in the table are the detection frequency in both
normal and 2F modes, this is the same as the reference frequency in normal mode and is
twice the reference frequency in 2F mode.
Range 2 3 4 5 6 7 8 9 10 11 12 13 14
RANG0 0 0 0 0 0 0 1 1 1 1 1 1 1
RANG1 0 0 1 1 1 1 0 0 0 0 1 1 1
RANG2 1 1 0 0 1 1 0 0 1 1 0 0 1
RANG3 0 1 0 1 0 1 0 1 0 1 0 1 0
Low Freq
25
kHz
48.8
kHz
97.6
kHz
195
kHz
390
kHz
781
kHz
1.56
MHz
3.12
MHz
6.25
MHz
12.5
MHz
25
MHz
50
MHz
100
MHz
High Freq 48.8
kHz
97.6
kHz
195
kHz
390
kHz
781
kHz
1.56
MHz
3.12
MHz
6.25
MHz
12.5
MHz
25
MHz
50
MHz
100
MHz
200
MHz
DVCE: Multiplexed Outputs
U613 and U619 are a cascaded pair of multiplexers, the output of which is at the
detection frequency F
D
. This output is buffered by U616 and goes to the Chop circuit on
84CMX.
U618 is a multiplexer whose output is at the reference frequency F
R
. This output is
synchronized with a 2
×
F
R
clock in U620 and U622. The output of U620 goes to the
phase-locked loop circuit on 84XRF, while the output of U622 goes to the Reference Out
circuit. U650 is a current-feedback amplifier with some feedback resistors included in
the package. R658, R659 make the part into a differential amplifier. R655, R678 and
R679 form an attenuator that also provides reverse termination. The output goes directly
to the front panel BNC connector Ref Out.
The low-frequency inputs to U618 come from U643 and TTL multiplexer U649. The
signals are converted from TTL to ECL levels using resistor networks R654/R674/R694
and R648/R668/R688. Similarly the low-frequency inputs to U619 come from U643 and
TTL multiplexer U645.