Stanford Research Systems SR844, User Manual

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6-20 Circuit Descriptions
SR844 RF Lock-In Amplifier
used for sensing the tuning voltage.
VTUN2
goes to the Range Select section of the
motherboard 84MBD.
P364 is used to null out offsets in the phase-locked loop. Any imbalance in the phase
comparators
U
and
D
levels requires the PLL to run at a compensating phase offset.
P364 is tuned till the PLL has zero phase offset.
XVCO: Voltage Controlled Oscillator
The input to this circuit is the tuning voltage
VTUNE
from the previous section. This
signal is filtered by R380–381, C380–381 and clamped by D381 (
≥
–0.4V) before it is
fed into the VCO U381. Note that the input network also provides some reverse filtering
to keep high frequency signals out of U344. The output of U381 is nom10dBm
between 200 and 400 MHz. The VCO output is split, one pair of signals goes to the
divider chain on 84DVC, the other pair goes to the synthesizer on 84MBD. The baluns
T385, T386 convert the single-ended VCO output into differential signals.
84DVC: Divider Chain Board
The 84DVC board is mounted just above the right rear portion of the motherboard. This
board contains the divider chain. Since the SR844 operates synchronously, all
instrument operations are clocked by signals derived from the reference frequency. The
divider chain takes the VCO output (200 – 400 MHz) and uses flip-flops and counters to
generate clock signals at (100 – 200 MHz), (50 – 100 MHz) all the way down to (24.4 –
48.8 kHz). The 84DVC board also contains multiplexers for selecting the appropriate
tap for various circuit functions and associated logic. The Reference Out driver is also
located on this board.
Document Number Sheet Schematic
DVCE 2 Divider Chain, Multiplexed and Fixed Outputs
DVCR 3 Power and Multiplexer Control Bits
DVCE: Divider Chain
400D
±
are the differential inputs from the VCO; these signals are AC coupled into
buffer U601. One pair of outputs goes through a delay line J601/J602 direct to one input
of the 2F multiplexer U624. The other output goes down the divider chain, buffer U603
then
÷
2 counter U604. As with subsequent stages, the outputs of U604 go to several
multiplexers in addition to going down the divider chain. This output is buffered by
U605 and divided by
÷
2 counter U606. Another buffer U607 delivers the signal (now
50–100 MHz) to a 3-stage counter U608, the
÷
8 output of this counter is in the range 6–
12 MHz. This signal is buffered by U611A and converted to TTL by comparator U638.
The TTL signal goes into 12-stage counter U643, which generates all the remaining
clocks down to 24.4 – 48.8 kHz.