Program instructions
7.6 Counters
S7-200 SMART
272
System Manual, V2.3, 07/2017, A5E03822230-AF
HSC0
HSC1
HSC2
HSC3
HSC4
HSC5
Description (used only when
HDEF is executed)
SM37.0
Not
support-
ed
SM57.0
Not
support-
ed
SM147.0 SM157.0 Active level control bit for Reset:
*
•
0 = Reset is active high
•
1 = Reset is active low
SM37.2
Not
support-
ed
SM57.2
Not
support-
ed
SM147.2 SM157.2 Counting rate selection for AB
quadrature phase counters
:*
•
0 = 4X counting rate
•
1 = 1X counting rate
* The default setting of the reset input is active high, and the AB quadrature phase counting rate is 4x
(or four times the input clock frequency).
Example: High-speed counter definition
LAD
STL
MAIN
On the first scan:
1.
Select the reset input to be active
high and select 4x mode.
2.
Configure HSC0 for AB quadrature
phase with reset input (mode 10).
Network 1
LD SM0.1
MOVB 16#F8, SMB37
HDEF 0, 10
HSC instruction enables counters, sets counting direction, and loads preset/current count values
The HSC instruction uses the control byte during execution. After you assign the counter and
the counter mode, you can program the dynamic parameters of the counter. Each high-
speed counter has a control byte in SM memory that allows the following actions:
●
Enabling or disabling the counter
●
Controlling the direction (modes 0 and 1 only), or the initial counting direction for all other
modes
●
Loading the current value
●
Loading the preset value