Program instructions
7.10 Interrupt
S7-200 SMART
330
System Manual, V2.3, 07/2017, A5E03822230-AF
7.10.5
Interrupt priority, queuing, and example program
Interrupt service
Interrupts are serviced by the CPU on a first-come-first-served basis within their respective
priority group. Only one user-interrupt routine is ever being executed at any point in time.
Once the execution of an interrupt routine begins, the routine is executed to completion. It
cannot be pre-empted by another interrupt routine, even by a higher priority routine.
Interrupts that occur while another interrupt is being processed are queued for later
processing. The following table shows the three interrupt queues and the maximum number
of interrupts they can store.
It is possible that more interrupts can occur than a queue can hold. Therefore, queue
overflow memory bits (identifying the type of interrupt events that have been lost) are
maintained by the system. The following table shows the interrupt queue overflow bits. You
should use these bits only in an interrupt routine because they are reset when the queue is
emptied, and control is returned to the scan cycle.
If multiple interrupt events occur at the same time, the priority (group and within a group)
determines which interrupt event is processed first. Once the highest priority has been
handled, the queue is examined to find the current highest priority event that remains in the
queue and the interrupt routine attached to that event is executed. This continues until the
queue is empty and control is returned to the scan cycle.
Maximum number of entries per interrupt queue
The following table shows all interrupt events, with their priority and assigned event number.
Queue
Queue depth for all S7-200 SMART CPU models
Communications queue
4
I/O interrupt queue
16
Timed interrupt queue
8
Interrupt queue overflow bits
Description (0 = No Overflow, 1 =
Overflow)
SM Bit
Communications queue
SM4.0
I/O Interrupt queue
SM4.1
Timed Interrupt queue
SM4.2
