Technical Description
S5-115F Manual
System response time:
Response time is the period between the input signal change on the process side and the output
signal change on the process side.
This time is typically the sum of the following elements ( Figure 2-4):
•
The inherent delay of the input module
•
The program scan time
•
The inherent delay of the output modules
Figure 2-4. Definition of the System Response Time
Module delays
PLC cycle n-1
PLC cycle n+1
Input signal on
the process side
Uniform value
in PII
Result in PIQ
Output signal
on the CPU side
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
a a a a a a a
Ouptut signal on
the process side
User
program n-1
Operating
system
User
program n
Operating
system
User program
n+1
PLC cycle n
System response time
2 x PLC scan time
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
a a a a a a a a
Input signal on
the CPU side
Under worst case conditions, the system response time is double the PLC scan time.
2-6
EWA 4NEB 811 6148-02