5
Addressing
5.1
Address Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 1
5.1.1
Digital Module Addresses
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 1
5.1.2
Analog Module Addresses
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 1
5.2
Slot Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 2
5.3
Handling Process Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 5
5.3.1
Accessing the PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 6
5.3.2
Accessing the PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 7
5.3.3
Direct Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 8
5.4
CPU Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 10
5.5
Process Interrupt Generation with the
6ES5 434-7LA12 Digital Input Module
. . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12
5.5.1
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 12
5.5.2
Initialization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 12
5.5.3
Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 13
5.5.4
Programming Example
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 - 15
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EWA 4NEB 811 6148-02