Table 206: Design resources
Path in ZIP archive
File
dslm_n_spi
dslm_n_bus
Resource
\ (root)
dslm_n_spi.qsf
dslm_n_bus.qsf
x
x
Project settings and time condi‐
tions
\wrapper
wrapper_n_spi.vhd
wrapper_n_bus.vhd
x
x
VHDL template for the top level
circuit "wrapper" for Altera Quar‐
tus II
\source
e_dslm_n.vhd
e_auxiliary.vhd
e_check8b10b.vhd
e_crc5.vhd
e_crc16.vhd
e_dec8b10b.vhd
e_dsl_core_top.vhd
e_dslmaster.vhd
e_dualport.vhd
e_enc8b10b.vhd
e_flag.vhd
e_framer.vhd
e_globals.vhd
e_int_ctrl.vhd
e_intg.vhd
e_master_pm.vhd
e_par_mrx.vhd
e_par_mtx.vhd
e_par_pm.vhd
e_pipeline.vhd
e_reset_sync.vhd
e_sampler.vhd
e_sequencer.vhd
e_sync_gen.vhd
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Encrypted VHDL modules
\source\ Exter‐
nal_Blocks
spi_ctrl.vhd
bus_ctrl.vhd
x
x
Open VHDL modules
\license
DSL_encr_license.dat
x
x
License file for use of the
encrypted VHDL project
NOTE
Please note: If you import the time lines from the associated qsf file into Quartus II, set
the following options in the "Advanced Import Settings" dialog box:
9
FPGA IP-CORE
158
T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
8017595/ZTW6/2018-01-15 | SICK
Subject to change without notice