SICK HIPERFACE DSL Technical Information Download

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"dsl_out"
"dsl_in"
"dsl_en"

Based on RS-485 specification, see appli‐
cation schematics

Typical signal transmission rate

9,375,000 baud

Drive interface

"online_status_d(15:0)"
"hostd_a(6:0)"
"hostd_di(7:0)"
"hostd_do(7:0)"
"hostd_r"
"hostd_w"
"hostd_f"

drive interface signals

SPI PIPE interface - optional, configurable by the user

"pipipe_clk"
"pipipe_miso"
"pipipe_ss"

Based on SPI specification

Maximum SPI clock

10 MHz

Control signals

Digital input – "sync"

Synchronization to drive clock

Sync signal cycle time

12.2 … 1950 μs

Minimum sync signal duration

40 ns

Maximum jitter sync frequency

2 system clock cycles, 26 ns

Digital output – "sync_locked"

Drive clock synchronization indicator

Digital output – "interrupt"

Interrupt configurable by the user, high
active

Digital output – "link"

DSL interface indicator, high active

Digital output – "fast_pos_rdy"

Indicator fast position value availability

Digital output – "dev_thr_err"

Indicator position estimator deviation
threshold crossed

Digital input – "bigend"

Byte sequence selection for register
addresses

Test signals

Digital output “estimator_on”

Indicator for active position estimator

Digital output “safe_channel_err”

Indicator for safety frame transmission
errors

Digital output “safe_pos_err”

Indicator for safe position update errors

Digital output “acceleration_err”

Indicator for transmission error of fast
position

Digital output “acc_thr_err”

Indicator for crossing of fast position error
counter threshold

Digital output “encoding_err”

Indicator for 8b/10b encoding transmis‐
sion fault

Table 185: Functional characteristics of the DSL Master IP Core

Parameter

Value

Units

Remarks

Minimum

Typical

Maxi‐
mum

System clock

74.9925

75.0000

75.0075 MHz

± 100 ppm

Characteristics of the interface

Wire transmission rate

9.375

MBd

FPGA IP-CORE

8017595/ZTW6/2018-01-15 | SICK

T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL

137

Subject to change without notice

Summary of Contents for HIPERFACE DSL

Page 1: ...T E C H N I C A L I N F O R M A T I O N HIPERFACE DSL Implementation ...

Page 2: ...r the non infringement of patent rights e g in the case of recommendations for circuit designs or processes The trade names listed are the property of the relevant companies HIPERFACE and HIPERFACE DSL are registered trademarks of SICK STEGMANN GmbH SICK STEGMANN GmbH Dürrheimer Strasse 36 78166 Donaueschingen Germany Tel 49 771 807 0 Fax 49 771 807 100 Internet http www sick com E mail info sick ...

Page 3: ...rface 22 5 2 SPI PIPE Interface 23 5 3 Control signals 24 5 4 Test signals 26 6 Register map 29 6 1 Explanation of the registers 29 6 2 Online Status D 30 6 3 DSL Master function register 32 6 4 Function register for the DSL Slave 55 7 Central functions 59 7 1 System start 59 7 2 System diagnostics 60 7 3 Fast position 61 7 4 Safe position Channel 1 66 7 5 Parameters Channel 67 7 6 Status and erro...

Page 4: ...e specification 148 9 5 Register assignment 150 9 6 Implementation of the IP Core for Xilinx Spartan 3E 6 151 9 7 Installation of the IP Core for Altera FPGAs 156 10 DSL component interoperability 161 10 1 Servo controller recommendations 161 10 2 Motor recommendations 164 10 3 Recommendations for connection line 166 10 4 Recommendations on installation site 168 11 Index 169 12 Glossary 170 13 Ver...

Page 5: ...s 66 22 Polling registers for the fast position in SYNC mode 66 23 Polling of rotation speed registers in SYNC mode 66 24 Polling the safe position 67 25 Reading from remote register 68 26 Long message characteristics 69 27 Example of a long message read command 72 28 Reset of the Parameters Channel 73 29 Acknowledgment of event bits 74 30 Tree structure of the resources database 87 31 Code disc p...

Page 6: ...RFACE DSL interface are described with the fol lowing documents Data sheet Operating instructions Errata document 2 3 HIPERFACE DSL for Motor Feedback Systems This document describes the use and implementation of the HIPERFACE DSL data pro tocol installed in motor feedback systems of servo drives HIPERFACE DSL is a purely digital protocol that requires a minimum of connection cables between freque...

Page 7: ...upply cable to the motor This means that no encoder plug connector to the motor and to the frequency inverter is necessary The cable length between the frequency inverter and the motor feedback system can be up to 100 m without degradation of the operating performance The digital HIPERFACE DSL protocol can be used for a variety of frequency inverter applications For the feedback cycle of the frequ...

Page 8: ...ate Array The available protocol logic enables free routing when installing the HIPERFACE DSL IP Core The protocol circuit can be installed along with the frequency inverter application on the same FPGA Choice between full duplex SPI SPI serial peripheral interface or parallel inter face between protocol logic and frequency inverter applications for standardized access to process data position rot...

Page 9: ...sfer speed to the frequency inverter cycle the overall transfer rate of the HIPERFACE DSL depends on the frequency inverter clock The protocol package is matched to the various lengths see figure 2 Provided the fre quency inverter cycle is long enough additional sampling points can be positioned in the frequency inverter cycle known as Extra packages The number of additional packages is programmed...

Page 10: ...60 13 33 12 8 125 12 50 10 16 62 5 12 50 5 40 25 12 50 2 37 to 84 27 to 12 2 27 to 12 2 1 Free running 11 52 In HIPERFACE DSL the data are transmitted over several channels Each individual channel is adapted to different requirements according to its content The cycle time of each individual channel varies with the length of the basic protocol package 3 PROTOCOL OVERVIEW 10 T E C H N I C A L I N F...

Page 11: ... 330 to 167 SensorHub channel External data 12 2 to 27 0 660 to 334 3 1 Process data channel The fast position value of the motor feedback system is transferred on the process data channel synchronously with the position requests that are controlled by the signal at the SYNC input of the frequency inverter cycle The process data channel is the fastest channel of the HIPERFACE DSL protocol Every pr...

Page 12: ...rpose Where there are deviations between the safe and the fast position values an error message is generated see chapter 5 4 2 In this case the protocol replaces the fast position with the estimated position Please see chapter 7 3 1 for details In each package of the safe channel a collection of status bits is transferred that reflects the error and warning condition of the motor feedback system N...

Page 13: ... transaction allows access to resources that have an influence on the HIPERFACE DSL protocol interface and are used for monitoring them This includes detailed status and error messages for the motor feedback system and indications of the signal strength on the DSL connection As a short message transaction is processed directly by the interface logic of the motor feedback system this transaction is...

Page 14: ... present at the DSL Master SYNC input Depending on the use of the SensorHub interface external data can therefore be sampled and transferred synchronously The protocol in the SensorHub Channel is not monitored by HIPERFACE DSL Apart from the monitoring of the data transfer quality there are no protocol mechanisms on this channel Figure 4 HIPERFACE DSL SensorHub interface 3 PROTOCOL OVERVIEW 14 T E...

Page 15: ...s of the following table 3 under worst case conditions of the application Table 3 Interface circuit Characteristic Value Units Transfer rate 20 MBaud Permitted common mode voltage 7 to 12 V Receiver Differential threshold voltage 200 mV Load resistance 55 Ohm Receiver running time delay 60 ns Sender running time delay 60 ns Sender power up delay 80 ns Sender power down delay 80 ns Sender rise time...

Page 16: ...mmended for the motor cable 4 1 2 Integrated cable two core cable For a connection via a two core cable integrated in the motor cable see chapter 4 3 the data cables must be provided with a transformer to raise the common mode rejec tion ratio To feed the supply voltage into the data cables choke coils are also required In connection with the associated table figure 6 below gives the specification...

Page 17: ...elp in attaining a system design optimized for transmission robustness During PCB design a good RF isolation for the interface circuit shall be achieved against the motor power circuit The two sides of the transformer TR1 have to be well separated from each other to avoid crosstalk Inside the servo controller the DSL signal lines shall be routed as short as possible and with good symmetry in the d...

Page 18: ...em via a special protocol logic circuit that is designated as the DSL Master The circuit is sup plied by SICK and must be installed in an FPGA component It is supplied as an Intellec tual Property Core IP Core The DSL Master IP Core is supplied in different forms depending on the FPGA vendor preferred by the user compiled netlist or encrypted VHDL If there is sufficient space in the FPGA being use...

Page 19: ...figurable interrupt link Output Connection indication pos_ready Output Position data availability indication sync_locked Output Position sampling resolution locked bigend Input Byte sequence choice fast_pos_rdy Output Fast position update indication sample Output DSL bit sampling information estimator_on Output Postion Estimator activated safe_channel_err Output Transmission error in safe channel ...

Page 20: ...uency inverter clock must be supplied to this input pin Please refer to table 8 for the signal specification This signal triggers position sampling of the DSL encoder The polarity of the edge can be programmed using the SPOL bit in the SYS_CTRL register As the frame cycle time must always be within a limited range a divider for the SYNC frequency has to be chosen accordingly The divider value need...

Page 21: ...cables see chapter 4 1 2 the motor cables are not listed Table 9 Technical data for the HIPERFACE DSL cable Characteristic Minimum Typical Maximum Units Length 100 m Impedance at 10 MHz 100 110 120 W DC loop resistance 0 1 W m Velocity ratio 0 66 c Propagation delay 5 ns m Limit frequency 25 MHz Maximum current per cable 0 25 A Operating temperature 40 125 C More information relating cable constru...

Page 22: ...rol signals Control signals Test signals Test signals Figure 9 DSL system interfaces Table 10 Interface functions Interface Function Drive interface Register based access to all DSL Master and DSL Slave functions relevant for the core frequency inverter application SPI PIPE Optional register based access to SensorHub Channel data Control signals DSL Master indication and control signals Test signa...

Page 23: ...inverter cycle the bandwidth of Drive interface is insufficient to access position and pipeline data or if the pipeline data is being processed by another frequency inverter application resource NOTE It should be noted that in every case the configuration of external sensor components at the sHub is carried out via the DSL Master Parameters Channel The SPI PIPE pro vides only one read access to th...

Page 24: ...so after spipipe_ss high 25 70 ns F Delay spipipe_miso after spipipe_clk high 25 70 ns 5 2 2 Read pipeline The SPI PIPE transaction Read Pipeline is used for access to the FIFO buffer values that contain the data and status of the SensorHub Channel Table 13 Read Pipeline transaction Symbol Meaning PIPE STATUS SensorHub Channel status see chapter 6 3 21 PIPE DATA SensorHub Channel data see chapter ...

Page 25: ...M register see chapter 6 3 3 and therefore indicates whether the DSL Master has produced a com munications link to a connected HIPERFACE DSL motor feedback system link is intended to be a control signal for an LED display but can also be used to con trol the start up performance see chapter 7 1 or for global error handling link is reset if communication faults are detected 5 3 4 FAST_POS_RDY signa...

Page 26: ...ystem Figure 12 Sample signal The sample signal can be used for eye diagrams to measure time and voltage margins during signal transmission When making the evaluation signal delays in the DSL Master must be taken into account The rising edge of the sample signal is offset by 40 ns from the line driver signal The time delay of the line driver must also be taken into account Typically this is 13 ns ...

Page 27: ... the safe position or sta tus see chapter 6 3 15 being invalid Such events are A coding error in transmission of the safe position A check sum error in transmission of the safe position The safe_channel_err signal can be used to carry out a statistical analysis of the incidence of errors in the DSL system 5 4 5 SAFE_POS_ERR signal safe_pos_err is a DSL Master digital output safe_pos_err is a DSL M...

Page 28: ...ING_ERR signal encoding_err is a DSL Master digital output The encoding_err signal is set if the underlying 8B 10B encoding of a DSL frame transmission is disturbed The encoding_err signal can be used to make a statistical analysis of the bit error rate of a DSL system 5 INTERFACES 28 T E C H N I C A L I N F O R M A T I O N HIPERFACE DSL 8017595 ZTW6 2018 01 15 SICK Subject to change without notic...

Page 29: ...h is intended for this The addressing of these registers is identical to the addressing of the registers in the DSL Master The answer to the trans action is however delayed and must be read individually see under Short message in chapter 7 5 1 figure 13 below shows via which interface a connection to which register block is estab lished DSL Master Primary functions Registers for all main functions...

Page 30: ...s The signal name of the Online Status is online_status_d with d indicating drive online_status_d is given in two bytes If an SPI block is used for interfacing the IP Core online_status_d is transmitted in each transaction in the first two bytes via the spi_miso output When a parallel bus interface is used for drive interface online_status_d has 16 dedicated output signals available NOTE It should...

Page 31: ...hat the safe position transmitted from the encoder is invalid 0 The last safe position received was correct Bit 1 DTE Deviation Threshold Error see chapter 5 4 3 1 Current value of deviation greater than the specified maximum 0 Current value of deviation smaller than the specified maximum Bit 0 PRST Protocol reset 1 IP Core has restarted the protocol 0 IP Core running Table 19 Online Status D Low ...

Page 32: ...OTE The addresses given below are referencing a big endian addressing For a table stating the register addresses depending on the endianness see chapter 9 5 Table 20 Description of the registers in DSL Master drive interface Addr Designation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value at reset 00h SYS_CTRL PRST MRST FRST LOOP PRDY SPPE SPOL OEN 0000 0000 01h SYNC_CTRL ES 0000 0001 03h MA...

Page 33: ...0 26h PC_BUFFER6 Parameters Channel byte6 0000 0000 27h PC_BUFFER7 Parameters Channel byte7 0000 0000 28h PC_ADD_H LID LRW LOFF LIND LLEN LADD9 8 1000 0000 29h PC_ADD_L LADD7 0 0000 0000 2Ah PC_OFF_H LID LOFFADD14 8 1000 0000 2Bh PC_OFF_L LOFFADD7 0 0000 0000 2Ch PC_CTRL LSTA 0 2Dh PIPE_S POVR PEMP PERR PSCI 0000 2Eh PIPE_D SensorHub FIFO output 0000 0000 2Fh PC_DATA Short message data 0000 0000 3...

Page 34: ...hows time of receipt of all position transmissions 0 pos_ready shows only the time of receipt of position transmissions following a control clock sync input Bit 2 SPPE SPI PIPE activation 1 SPI PIPE activated Access to pipeline status and data via SPI PIPE The registers PIPE_S and PIPE_D are read as 0 0 SPI PIPE deactivated Access to pipeline status and data via the registers PIPE_S and PIPE_D Bit...

Page 35: ...n process data channel 2 Unknown special characters in the protocol package 2 Any identified error in Safe Channel 1 6 Any identified error in Safe Channel 2 8 Correct synchronization in Safe Channel 1 Correct CRC value in Safe Channel 1 Quality monitoring is initiated with the value 8 The maximum quality monitoring value is 15 This is the standard value during opera tion NOTE Particular attention...

Page 36: ...are set when the corresponding status arises They are only set again if the corre sponding status disappears and then arises once more This is the standard action The level sensitive bits set a bit as long as the corresponding status exists NOTE It should be noted that all event register bits are also transferred to Online Status D see chapter 6 2 and chapter 7 6 2 The event bits are not static th...

Page 37: ...he DSL connection If this error occurs frequently the wiring of the DSL connection should be checked If this error occurs continuously there is probably an error in the motor feedback system CAUTION When this error occurs the fast position is updated by the estimator see chapter 7 3 1 Bit 2 VPOS Safe position error 1 Sensor error 0 The safe position is correct This error usually indicates an encod...

Page 38: ... that the transmission of an answer from the DSL Slave to the last long message failed The frequency inverter application must send the long mes sage again Bit 3 Not implemented Read as 0 Bit 2 QMLW Quality monitoring low value warning 1 Quality monitoring value see register 03h below 14 0 Quality monitoring value greater than or equal to 14 This warning indicates that a transmission error occurre...

Page 39: ...SCE VPOS SUM FRES FREL MIN ANS QMLW Status DSL Slave Reg 18h SUM7 SUM0 SUM1 SUM3 SUM5 SUM4 SUM2 SUM6 INT output OR Event Mask Reg 06h Reg 07h MPRST MDTE MPOS MSCE MVPOS MSUM MFRES MFREL MMIN MANS MQMLW Status Mask Reg 08h MSUM7 MSUM0 MSUM1 MSUM3 MSUM5 MSUM4 MSUM2 MSUM6 Figure 14 Interrupt masking NOTE It should be noted that the SUM bit is an OR connection of all bits of the status bit is an OR co...

Page 40: ...X 0 W 0 W 0 X 0 MMIN MANS MQMLW MFREL Bit 7 Bit 0 Bit 7 6 Not implemented Read as 0 Bit 5 MMIN Mask for message initialization confirmation 1 The acknowledgment for the initialization of a DSL Slave message sets the inter rupt signal 0 The acknowledgment for the initialization of a DSL Slave message does not set the interrupt signal Bit 4 MANS Mask for erroneous answer to long message 1 A transmis...

Page 41: ...t status the corresponding status summary bit does not set the SUM event monitoring and the signal at the interrupt pin 6 3 7 Edges The EDGES edge register contains the time control for the DSL cable bit sampling and can be used to monitor the connection quality Each individual edge register bit is set if at system start up an edge of the test signal is detected during the time period of the corre...

Page 42: ...e signal round trip delay of cable and transceivers in bits This value enables a rough estimate of cable length to be made The value for Line Delay does not change after the start up phase A fresh value for Line Delay is only measured after a forced reset of the protocol table 22 below shows the relationship between the value in Line Delay and the cable length of the DSL connection Table 22 Cable ...

Page 43: ... the release date register encodes the release month as binary number 01h January 0Ch December The third returned byte from the release date register encodes the release day as binary number 01h 1st 1Fh 31st Every reading to the RELEASE register after the third byte repeats the third returned byte To reset the RELEASE register a new reading of the VERSION register is required While one of the inte...

Page 44: ...er 6 3 12 standard value 11 bits Bit 3 to 0 Acc 8 Length of the acceleration value transmitted standard value 11 bits minus 8 6 3 12 Fast position The POS registers for the fast position contain the value of the motor feedback system connected This position is generated incrementally from the safe position at start up and is updated with every protocol frame After every eight protocol frames the f...

Page 45: ...h 40 bits incrementally generated 6 3 13 Speed The VEL speed registers contain the speed values of the connected motor feedback system This value is calculated as a Δ position from the acceleration value ΔΔposi tion transmitted on the process data channel and the currently updated protocol frame see chapter 3 The speed sampling point is determined by the ES value of the SYNC_CTRL register The unit...

Page 46: ...3 Bit 3 Bit 1 Bit 0 Reg 43h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 1 Bit 0 Reg 44h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 1 Bit 0 Reg 45h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 1 Bit 0 Reg 46h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 1 Bit 0 Reg 47h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 1 Bit 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 15 DSL Slave status and summary A bit that ha...

Page 47: ...ange that the motor feedback system has actually measured All other higher value bits are read as 0 The number of measurable bits can be taken from ENC_ID bits 9 to 0 in the ENC_ID0 to 2 regis ters If Sign is set in the ENC_ID register the value of the safe position is given signed in the two s complement The units of the position value are steps These registers are write protected Register 19h Sa...

Page 48: ...o calculate the CRC is shown in the following figure SAFE_SUM VPOS 39 32 VPOS 31 24 VPOS 23 16 VPOS 15 8 VPOS 7 0 Figure 16 Sequence of the bytes to calculate the CRC Register 1Eh CRC of the safe position byte 1 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 CRC of the safe position byte 1 Bit 15 Bit 8 Register 1Fh CRC of the safe position byte 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 CRC of the safe position byte 0 Bi...

Page 49: ...20h Parameters Channel buffer byte 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Parameters Channel byte 0 Bit 63 Bit 56 Register 21h Parameters Channel buffer byte 1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Parameters Channel byte 1 Bit 55 Bit 48 Register 22h Parameters Channel buffer byte 2 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Parameters Channel byte 2 Bit 47 Bit 40 Registe...

Page 50: ...ameters Channel buffer contains the error code in bytes 0 and 1 associated with this status see chapter 7 6 6 Register 28h Long message address byte 1 R 1 W 0 R W 0 W 0 W 0 W 0 W 0 W 0 LID LRW LOFF LIND LLEN LADD9 LADD8 Bit 15 Bit 8 Register 29h Long message address byte 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LADD7 0 Bit 7 Bit 0 Bit 15 LID Long message identification This is a read only bit that will a...

Page 51: ...coder resource Only write access is possible for these registers Register 2Ah Long message address offset byte 1 R 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LID LOFFADD14 8 Bit 15 Bit 8 Register 2Bh Long message address offset byte 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LOFFADD7 0 Bit 7 Bit 0 Bit 15 LID Long message identification The value must be 1 Bit 14 0 LOFFADD14 0 Long message offset value The 15 bit offset...

Page 52: ...ter Register 2Dh SensorHub Channel status X 0 X 0 X 0 X 0 R 0 R 0 R 0 R 0 POVR PEMP PERR PSCI Bit 7 Bit 0 Bit 7 4 Not implemented Read as 0 Bit 3 POVR SensorHub Channel overflow 1 The capacity of the 8 byte FIFO buffer for SensorHub Channel data was exhausted and since the last read process values have been discarded 0 The capacity of the FIFO buffer for SensorHub Channel data is not yet exhausted...

Page 53: ...dest value is discarded and the POVR bit in PIPE_S is set If a read request is issued when the buffer is empty the PEMP bit in PIPE_S is set and the value 00h is transmitted PIPE_D is only accessible as a register of the DSL Master if SPI PIPE is deactivated SPPE in the SYS_CTRLregister is deleted Otherwise the value of PIPE_D is transmitted via SPI PIPE as the second byte of each read request see...

Page 54: ...acc_thr_err will be set to 1 Register 38h Fast position error counter X 0 X 0 X 0 R W 0 R W 0 R W 0 R W 0 R W 0 CNT4 CNT3 CNT2 CNT1 CNT0 Bit 7 Bit 0 Bit 7 5 Not implemented Read as 0 Bit 4 0 CNT4 CNT0 Position error count threshold for acc_thr_err Read 5 bit value of count of transmitted fast position values with consecutive transmis sion errors Write 5 bit value for threshold of acc_thr_err 6 3 2...

Page 55: ... DSL Slave The remote registers of the DSL Slave encoder are mirrored in the DSL Master under the addresses 40h to 7Fh These registers are accessible using short message trans actions see chapter 7 5 1 NOTE It should be noted that the DSL Slave register can only be accessed via 8 bit address ing The bigend option does not affect the Slave register address allocation The minimum number of remote re...

Page 56: ...e figure 14 In this way the appro priate groups can react rapidly to slave statuses NOTE Bits in the encoder status register can only be set by the DSL Slave and only deleted by the frequency inverter application acknowledgment Table 27 Encoder status and summary register Encoder status SAFE_SUM bit DSL Master 36h ENC_ST0 40h SUM0 ENC_ST1 41h SUM1 ENC_ST2 42h SUM2 ENC_ST3 43h SUM3 ENC_ST4 44h SUM4...

Page 57: ...the particular DSL Slave installation Generally the speci fication in chapter 7 6 3 applies 1 Error event or warning status 0 Encoder in normal status 6 4 2 Slave RSSI The SRSSI register for indicating the received signal strength at the slave Slave Received Signal Strength Indicator RSSI provides an indication of the strength of the signal arriving at the slave The value of the register is only u...

Page 58: ...d to carry out connection tests on behalf of the DSL Slave The register can be written to and read externally without this affecting the DSL interface On start up the register is initialized with the DSL Slave interface hardware version NOTE This register can also be used for multi axis implementation For more information please see chapter Register 7Fh Slave Ping R W 0 R W 0 R W 0 R W 0 R W 0 R W...

Page 59: ...o further transmission error Protocol reset PRST 1 Power on Reset sequence OEN 1 Error acknowledged No further transmission error ES 0 Transmission error Encoder error Transmission error Encoder error Several transmission errors Figure 17 Status table for DSL system start Individual conditions are described in table 28 Table 28 Conditions at DSL system start Status Prerequisite Indication DSL Mast...

Page 60: ...blished If this bit remains deleted for longer than the expected start up time see encoder datasheet there is a fundamental problem in the connection between the frequency inverter and the motor feedback system Check whether the encoder is supplied with power Using an oscilloscope also check whether any level changes in the transmission fre quency range can be identified over the data cables betwe...

Page 61: ...s also possible For this the event bits QMLW and PRST must be polled These bits indicate QM sinking below a value of 14 poor quality or a broken connection if QM has a value of 0 or RSSI has a maximum value of 1 The following table contains the possible conditions Table 29 Values for quality monitoring and RSSI Quality monitoring value QMLW PRST Connection status LINK 15 0 0 Good connection qualit...

Page 62: ...POS flag 7 3 1 Estimator The estimator is implemented for providing an estimated fast position when the regular process provides wrong or no position at all The estimator is turned on because of the following reasons While operating under harsh conditions sometimes the encoder position cannot be sampled correctly e g mechanical shock In these cases the encoder will transmit a position not valid ch...

Page 63: ...olution Here mantissa is the value stored in bits 5 0 and resolution is defined as per the fol lowing table Table 30 Resolution of fast position acceleration boundary Bit 7 6 Resolution 00 256 01 64 10 16 11 4 The ACCLSB value is the resolution of the DSL fast position channel which can be calcu lated as ACCLSB 2 2Pres T2 hframe rad s2 with Pres as position resolution per turn in number of bits an...

Page 64: ...d values is explained in figure 19 and figure 20 Figure 19 Polling of position registers in free running mode Figure 20 Polling of rotation speed registers in free running mode 7 3 3 SYNC mode In SYNC mode the DSL Master depends on a prepared cyclic control signal This control signal triggers position measurements and enables polling of position and rotation speed values synchronously with the con...

Page 65: ...lae Symbol Description tSync Cycle time of the pulse signal at the SYNC input tMin Minimum cycle time for the transmission of DSL frames 11 95 µs tMax Maximum cycle time for the transmission of DSL frames 27 00 µs table 32 below contains typical cycle times for the control signal and the valid ranges of ES divider values Table 32 Cycle times for SYNC signals and valid ES values Frequency of the SY...

Page 66: ...fast reading of the position The rotation speed of the motor feedback system can be read in the same way The rotation speed is also measured and transmitted synchronously with the sync signal This is explained in figure 23 Figure 23 Polling of rotation speed registers in SYNC mode 7 4 Safe position Channel 1 The motor feedback system safe position is transmitted as a complete absolute posi tion Th...

Page 67: ...egis ters are addressed in the same way as DSL Master registers As the values of remote registers are transmitted via the Parameters Channel and hence via the DSL cables the delay between polling and answer for short message transactions depends on the connection cables of the systems in question Unlike DSL Master registers the frequency inverter application must wait for the answer to arrive Alth...

Page 68: ... the motor feedback system takes place by long message transactions on the Parameters Chan nel The organization and scope of the resources depend on the particular DSL Slave and DSL encoder installation A long message is triggered by setting the corresponding long message registers PC_ADD_H L PC_OFF_H L PC_CTRL and for write operations PC_BUFFER0 7 The result where present is recorded in the PC_BU...

Page 69: ... sheet for individual DSL encoders A long message is triggered by the setting of the corresponding PC_BUFFER PC_ADD PC_OFFand PC_CTRL 20h to 2Ch registers in the DSL Master Whilst the motor feedback system is processing a long message the FREL flag in the EVENT_L 05h events register is deleted Once the processing is finished this flag is set once more to indicate readiness to process a fresh long ...

Page 70: ...he DATA register are used Table 34 DATA register areas LEN value Data length DATA register used 0 00b 0 bytes No data transfer 1 01b 2 bytes PC_BUFFER0 PC_BUFFER1 2 10b 4 bytes PC_BUFFER0 PC_BUFFER1 PC_BUFFER2 PC_BUFFER3 3 11b 8 bytes PC_BUFFER0 PC_BUFFER1 PC_BUFFER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 The R W long message characteristic is used to determine whether a read or wr...

Page 71: ...purpose for which direct or indirect addressing is used The LEN characteristic determines the data length of the long message table 34 describes the use of this characteristic LEN must correspond to the permitted values applicable to the resource addressed see chapter 8 2 If these values are not observed the long message in the motor feedback system will be ended and a corresponding error message ...

Page 72: ... protocol automatically begins cyclic repetition of the transmission There is no limit to the number of repetitions and the user must decide when to issue a message reset If the DSL Master receives no acknowledgment of the successful reception of a long message from the DSL slave the protocol automatically begins a cyclic repetition of the transmission until such an acknowledgment is received This...

Page 73: ...L motor feedback system see chapter 8 2 To be able to use the Parameters Channel again in case of a pending short message or long message that is blocking the corresponding message channel the user appli cation must trigger a Message reset of the Parameters Channel see chapter 6 3 1 This reset does not affect position measuring or the transmission of position data The reset sequence for the Parame...

Page 74: ...itical motor feedback system error messages Recommendations for error handling can be found in chapter 6 3 4 The EVENT_L register contains all motor feedback system warning and status mes sages Recommendations for error handling can be found in chapter 6 3 4 All errors and warning conditions indicated in the event registers must be acknowl edged by deletion of the corresponding error bits The DSL ...

Page 75: ...tion detailed motor feedback system errors and warnings are indicated in the SUMMARY status summary register 18h see chapter 6 3 14 Each individual bit of the register indicates an error status of a functionality in the motor feedback system see table 41 The safety relevance of all of these error groups is precisely described in this table It should be noted that the reading of detailed motor feed...

Page 76: ...k system errors are grouped table 42 below contains all error messages and recommendations for error handling Depending on product family only some of the following errors might be reported Please consult individual product data sheets for availability of error messages Within the column Severity the different information is classified for general drive con troller reactions The column Required re...

Page 77: ...it can be handled as a minor severity error and no action required EEx37 Cross check Error Critical p Cross check of the two safety channels failed The drive system must be placed in a safe condition Action SW reset of the encoder 6 EKx36 EFx50 EDx35 Counter Error Critical p Position quadrant counter has detected an invalid sequence of signals Occurrence during opera tion leads to a permanent erro...

Page 78: ...as an alternative to position measurement if this error arises for the fast position In this case the significantly slower refresh cycle of the safe position must be considered If the error persists there is prob ably a general hardware or mechanical failure Inform cus tomer service 4 EKx36 EFx50 EDx35 Position Tracking Filter Error Minor np The sine cosine signals got a big distortion and the sig...

Page 79: ...eration or shaft was turned while the link was not active No action required Fault is not permanent and encoder recovers automati cally This error will likely will lead to other errors Possible causes mechani cal shocks or hardware faults If the error persists there is probably a general hard ware or mechanical failure Inform customer service 0 All Protocol Reset Indication Minor np Indicates that...

Page 80: ... ware faults magnet clip faults or gear wear out NOTE A multi turn synchro nization diagnostic cannot reliably detect gear synchro nization faults over extended time After first indication of this fault gear synchronization can wear out even more and result in undetected false position output The drive system must be placed in a safe condition Action immediate replace ment of encoder 1 All Multi t...

Page 81: ... are present 3 All Standard Parame ter Error Critical p There were errors in the inter nal encoder EEPROM parame ter or diagnosis that could not be rectified The drive system must be placed in a safe condition Action SW reset of the encoder 2 All Safety Parame ter Error Critical p The drive system must be placed in a safe condition Action SW reset of the encoder If error persists potential EEPROM ...

Page 82: ...was out of specification No action required Check application for higher speeds than speci fied Possibly reduce speed 2 All Critical Supply Voltage Minor np Supply voltage was out of specification No action required Check encoder power sup ply conditions If error persists after ensur ing the input power supply potential hardware failures are present and immediate replacement of the encoder is requ...

Page 83: ...EEPROM Potential cause may indicate EMC problems or corrupted file system due to previous power down during write access or just simply incorrect access parameters Check and retry command 2 All Resource access error Minor np Error when accessing an inter nal resource Potential cause may indicate EMC problems excessive number of EEPROM write cycles or wrong timing of power cycle vs EEPROM write acc...

Page 84: ...ag which are provided as a further digital output of the DSL master see also chapter 5 4 2 It indicates that the fast position value is invalid and the current value is supplied by the position estimator see chapter 7 3 1 For statistical analyses of the stability of the position reading this signal can be monitored in reference to a defined time base In this case it is possible to identify changes...

Page 85: ...he value of the PC_BUFFER1 register corresponds to the error code in the ENC_ST encoder status register see chapter 6 4 1 Table 43 Long message error codes PC_BUFFER1 PC_BUFFER0 Meaning of the error code 40h 10h Resource address not installed in the encoder 11h Incorrect length for resource access given 12h Incorrect length for direct resource access given 13h Offset address too high 14h Invalid o...

Page 86: ... Access to resources Access to the resources of a DSL motor feedback system is possible in two ways This section also describes how resource definitions can be read by direct access 8 1 1 Access by means of an index Each individual resource is defined by a unique resource index RID A long message can be directed at the associated resource by using the RID as the address characteristic see chapter ...

Page 87: ...message for reading a linked node are listed in table 44 Table 44 Parameters for node access Characteristic Value Description DATA MOTOR FEEDBACK SYSTEM RESOURCES 8 8017595 ZTW6 2018 01 15 SICK T E C H N I C A L I N F O R M A T I O N HIPERFACE DSL 87 Subject to change without notice ...

Page 88: ...of the resource The desired value is selected by the user by setting a corresponding offset address Please note that for different encoders the time overrun values can be different There fore it is recommended to check the time overrun values prior to reading The values provided in the resources list are only examples table 45 below sets out all possible access methods direct and indirect and thei...

Page 89: ... that the defining values of the resources that have been laid down in a motor feedback system have priority over the values published in this manual 8 2 Resources list The following sections contain possible resources installed in a DSL motor feedback system NOTE It should be noted that the motor feedback system position and rotation speed values are process values and access to these values is d...

Page 90: ...nistic Resource 00h Node indicator index 16 bit data type 01h 02h Void no data Bit 1 true 0 false 03h 8 bit unsigned 04h 16 bit unsigned 05h 32 bit unsigned 06h 64 bit unsigned 07h 8 bit with sign 08h 16 bit with sign 09h 32 bit with sign 0Ah 64 bit with sign 0Bh String character chain 10h to 4Fh Data structure with data length 0 to 63 bytes If the size of a resource gives a higher byte total than...

Page 91: ...tor feedback system electronic type label Direct read access to the designation node returns the defining values Table 49 Identification node defining values Defining value Offset Value RID 001h Resource name 0 IDENT Data size 1 2 Read access level 2 0 Write access level 3 15 Time overrun 4 75 Data type 5 00h node indicator Mandatory yes Indirect read access to the identification node returns info...

Page 92: ...el 2 0 Write access level 3 15 Time overrun 4 75 Data type 5 00h node indicator Mandatory yes Indirect read access to the administration node returns information on linked nodes see table 47 8 3 5 Counter node The counter node contains indicators to all resources associated with the user defined counter Direct read access to the counter node returns the defining values Table 52 Counter node defini...

Page 93: ...the defining values Table 54 Data storage node defining values Defining value Offset Value RID 006h Resource name 0 SENSHUB Data size 1 2 Read access level 2 0 Write access level 3 15 Time overrun 4 75 Data type 5 00h node indicator Mandatory yes Indirect read access to the SensorHub node returns information on linked nodes see see table 47 page 90 8 4 Identification resources The identification r...

Page 94: ...FER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_OFF_H PC_OFF_L PC_CTRL Write 54 80 00 00 01 Wait for FREL 1 Read Type of encoder 8 4 2 Resolution The resolution value defines the number of steps per rotation of the encoder rotary encoder or the length of a measurement step in multiples of 1 nm linear encoder Direct read access to resolution returns the defining values Table 58 Resolution defining ...

Page 95: ...gned Mandatory yes The measurement range is given as a 32 bit unsigned value For this resource access to the offset base is not meaningful as the size of the resource data is smaller than the maximum for a long message transaction Table 61 Reading the measurement range Transaction Register PC_BUFFER0 PC_BUFFER1 PC_BUFFER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_...

Page 96: ...PC_OFF_L PC_CTRL Write 7C 83 00 00 01 Wait for FREL 1 Read Characters 1 to 8 of the type name Write 7C 83 00 08 01 Wait for FREL 1 Read Characters 9 to 16 of the type name Write 74 83 00 10 01 Wait for FREL 1 Read Characters 17 to 18 of the type name 8 4 5 Serial number This resource indicates the serial number of the encoder The serial number is stored in ASCII format with a maximum length of 10 ...

Page 97: ...The firmware version is stored in ASCII format with a maximum length of 16 characters the hardware version is in the same format with a maximum of 4 characters Unallocated characters are stored with the ASCII code 00h Direct read access to device version returns the defining values Table 66 Device version defining values Defining value Offset Value RID 085h Resource name 0 FWREVNO Data size 1 20 R...

Page 98: ...urce indicates the firmware date of the encoder The firmware date is stored in ASCII format with a maximum length of 8 characters Direct read access to firmware date returns the defining values Table 69 Firmware date defining values Defining value Offset Value RID 086h Resource name 0 FWDATE Data size 1 8 Read access level 2 0 Write access level 3 15 Time overrun 4 70 Data type 5 0Bh string Mandat...

Page 99: ...ining values Defining value Offset Value RID 087h Resource name 0 EESIZE Data size 1 2 Read access level 2 0 Write access level 3 15 Time overrun 4 70 Data type 5 04h 16 Bit unsigned Mandatory yes For this resource access to the offset basis is not meaningful as the resource data can be read using a long message transaction Table 73 Reading the EEPROM size Transaction Register PC_BUFFER0 PC_BUFFER...

Page 100: ...0 0100 0111 1110b 047Eh 40 0 C 1111 1110 0111 0000b FE70h The temperature range values are given in the following format Table 76 Temperature range definition Byte Value Description 3 2 2730 to 10000 Maximum permitted encoder temperature in 0 1 C 1 0 2730 to 10000 Minimum permitted encoder temperature in 0 1 C By accessing offset basis only one of two temperature range values can be given Table 77...

Page 101: ...inition Byte Value Description 1 0 2730 to 10000 Current temperature value in 0 1 C For this resource access to the offset basis is not meaningful as the resource data can be read using a long message transaction Table 81 Reading the encoder temperature Transaction Register PC_BUFFER0 PC_BUFFER1 PC_BUFFER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_OFF_H PC_OFF_L P...

Page 102: ...ed sensor monitor value is outside either one of the range limits an error is indicated see chapter error group 3 error number 1 Direct read access to sensor monitor returns the defining values Table 82 Sensor monitor defining values Defining value Offset Value RID 0C3h Resource name 0 product specific Data size 1 product specific Read access level 2 0 Write access level 3 15 Time overrun 4 70 Dat...

Page 103: ... supply voltage 0000h 2 Minimum supply voltage 0002h 2 Maximum supply voltage Table 86 Reading the supply voltage range Transaction Register PC_BUFFER0 PC_BUFFER1 PC_BUFFER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_OFF_H PC_OFF_L PC_CTRL Write 58 C4 00 00 01 Wait for FREL 1 Read Min voltage Max volt age 8 5 6 Supply voltage This resource indicates the supply volt...

Page 104: ...y volt age 8 5 7 Rotation speed range This resource indicates the permitted maximum shaft rotation speed for rotary DSL motor feedback systems given in the product data sheet Direct read access to rotation speed range returns the defining values Table 90 Rotation speed range defining values Defining value Offset Value RID 0C6h Resource name 0 SPEEDRNG Data size 1 2 Read access level 2 0 Write acce...

Page 105: ...to rotation speed returns the defining values Table 93 Rotation speed defining values Defining value Offset Value RID 0C7h Resource name 0 SPEED Data size 1 2 Read access level 2 0 Write access level 3 15 Time overrun 4 70 Data type 5 04h 16 Bit unsigned Mandatory no The rotation speed value is stored as a 16 bit unsigned value The rotation speed value units are 1 rotation per minute min 1 It shou...

Page 106: ... stored as an unsigned 16 bit value The accelera tion value units are 1000 rad s It should be noted that the current acceleration value can be derived from the rotation speed process value in the process data channel see chapter 7 3 The acceleration range value is given in the following format Table 97 Acceleration range definition Byte Value Description 1 0 0 to 65535 Maximum permitted rotational...

Page 107: ... stored every 20 minutes in a non volatile memory CAUTION If the remaining task lifetime falls to 0 the encoder continuously issues error message 22 safety error If this is the case the encoder must be replaced Examples of time values Table 100 Examples of lifetime Duration Resource value bin Resource value hex 10 min 0000 0000 0000 0000 0000 0000 0000 1010b 0000 000Ah 200 hours 0000 0000 0000 000...

Page 108: ...on see chapter 7 5 In addition errors are stored in the non volatile memory of the DSL motor feedback system In addition those errors identified when the establishment of a connection to the fre quency inverter application failed are also stored in the error protocol This resource provides an overview of these errors A DSL motor feedback system can store a set number of errors in its error protoco...

Page 109: ... that the highest offset address that can be given depends on the maximum number of error protocol entries for the particular product Table 106 Offset selection for the error protocol Offset value Length of the message Return values 00 00h 8 Number of stored error messages 00 01h 8 First part of the most recently occurring error 01 01h 8 Second part of the most recently occurring error 00 02h 8 Fi...

Page 110: ...ange limits and the resolution of the histogram are given Table 109 Encoder parameter histograms definitions Encoder parameters Min class Max class Width of histogram class Temperature 40 C 120 C 10 C Sensor monitor product specific product specific product specific Supply voltage 6 0 V 14 0 V 1 0 V Rotation speed 0 to 500 min 1 10 000 min 1 500 min 1 The values of the usage histograms are each st...

Page 111: ...to 90 C 0Dh 90 to 100 C 0Eh 100 to 110 C 0Fh 110 to 120 C 10h 120 C 11h Sensor monitor product specific see product data sheet product specific see product data sheet Supply voltage 6 0 V 00h 6 0 to 7 0 V 01h 7 0 to 8 0 V 02h 8 0 to 9 0 V 03h 9 0 to 10 0 V 04h 10 0 to 11 0 V 05h 11 0 to 12 0 V 06h 12 0 to 13 0 V 07h 13 0 to 14 0 V 08h 14 0 V 09h MOTOR FEEDBACK SYSTEM RESOURCES 8 8017595 ZTW6 2018 ...

Page 112: ...et product specific see product data sheet The offset value must be given in the following format Table 112 Selection of the histogram offset Bits Value Definition 0 to 7 00h to FFh Identification of histogram class 8 to 11 0h 1h 2h 3h 4h Request temperature Request sensor monitor Request supply voltage Request rotation speed Request code disk position Table 113 Reading histogram entries Transacti...

Page 113: ...rce name data size data type and data format are specified in the product data sheet 8 7 Code disk position This resource indicates the current value of the code disc position of bearing less or kit encoders The resource can be used for monitoring correct assembly during mounting of the encoder to a motor During life time it also helps monitoring correct usage of the encoder e g due to axial motor...

Page 114: ...atory no Resource name data size data type and data format are specified in the product data sheet 8 8 Administration resources The administration resources of the DSL motor feedback system provide access to the encoder options settings 8 8 1 Reset shut down With this resource an encoder reset or shut down can be executed These sequences are required to validate certain changes save encoder operat...

Page 115: ...relevant data are saved e g lifetime information usage histograms NOTE It should be noted that in case of a reset the initializing time of the encoder as well as the maximum resource time overrun need to be taken into account This means that the encoder will start communicating only after this time has passed NOTE It should be noted that after shut down the encoder no longer reacts to any command ...

Page 116: ...itted value The position value to be allocated to the current shaft position is transmitted as an unsigned 40 bit value Only values in the measurement range of the DSL motor feedback system are valid During a read access the offset value currently being used is transmitted in the same format The position value for this command must be given in the following format Table 120 Set position definition...

Page 117: ... with which the appropriate level can be set Table 123 Access levels and standard access keys Access level Standard access key Usage 0 No access key necessary Publicly accessible system functions 1 31 31 31 31h Protected system functions operator level 2 32 32 32 32h Protected system functions maintenance level 3 33 33 33 33h Protected system functions authorized client level 4 34 34 34 34h Protec...

Page 118: ...hange access key returns the defining values Table 127 Change access key defining values Defining value Offset Value RID 105h Resource name 0 CHNGKEY Data size 1 8 Read access level 2 15 Write access level 3 0 Time overrun 4 90 Data type 5 18h structure with 8 bytes Mandatory yes To change the access key both the old and the new access keys for the target access level as well as the access level i...

Page 119: ...rded in the error protocol see chapter 8 5 11 Direct read access to user defined warnings returns the defining values Table 131 User defined warnings defining values Defining value Offset Value RID 107h Resource name 0 UWARNING Data size 1 8 Read access level 2 0 Write access level 3 2 Time overrun 4 90 Data type 5 18h structure with 8 bytes Mandatory no A user defined warning is configured by sel...

Page 120: ...d warning is to be processed and whether the configuration bits or the value are affected Table 134 User defined warning offset value Offset value Meaning 00h Configuration bits for user defined warning 1 01h Configuration bits for user defined warning 2 0Fh Configuration bits for user defined warning 16 10h Threshold bit mask for user defined warning 1 11h Threshold bit mask for user defined warn...

Page 121: ...his function with care NOTE It should be noted that lifetime information the error protocol and the usage histogram are not affected by this command Direct read access to factory settings returns the defining values Table 136 Factory settings defining values Defining value Offset Value RID 108h Resource name 0 FACRESET Data size 1 8 Read access level 2 15 Write access level 3 2 Time overrun 4 255 ...

Page 122: ...3 Time overrun 4 90 Data type 5 04h 16 Bit unsigned Mandatory yes The user defined encoder index can be between 0 and 15 Inputting a higher value will cause an error message The user defined encoder index is given in the following format Table 140 User defined encoder index definition Byte Value Description 7 to 2 Reserved for later use 1 0 0 to 15 Other values Requested user defined encoder index...

Page 123: ... POSFILT Data size 1 4 Read access level 2 0 Write access level 3 3 Time overrun 4 90 Data type 5 05h 32 bit unsigned Mandatory no The position filter is set in the following format Table 143 Position filter definition Byte Value Description 3 to 0 3000 to 37500 Mechanical filter limit frequency measured in rotations per minute rpm A previously set position filter can be identified using a read ac...

Page 124: ...FFh Value of the user defined counter For this resource access to the offset basis is not meaningful as the resource data can be read using a long message transaction Table 147 Reading the counter Transaction Register PC_BUFFER0 PC_BUFFER1 PC_BUFFER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_OFF_H PC_OFF_L PC_CTRL Write 59 20 00 00 01 Wait for FREL 1 Read Counter ...

Page 125: ...Direct read access to reset counter returns the defining values Table 150 Reset counter defining values Defining value Offset Value RID 122h Resource name 0 RESETCNT Data size 1 0 Read access level 2 15 Write access level 3 1 Time overrun 4 105 Data type 5 01h empty Mandatory no The reset is carried out using a write command to this resource that contains no data length of the long message 0 Table...

Page 126: ... defining values Table 152 Load file defined values Defining value Offset Value RID 130h Resource name 0 LOADFILE Data size 1 8 Read access level 2 15 Write access level 3 1 Time overrun 4 130 Data type 5 0Bh string Mandatory yes It should be noted that only one file can be loaded at a time When loading a new file any hitherto loaded file is discarded A file remains loaded until another file is lo...

Page 127: ...BUFFER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_OFF_H PC_OFF_L PC_CTRL Write F I L E 1 00 00 00 1D 30 00 00 01 Wait for FREL 1 Read 8 10 2 Read write file Read and write access to a user file is possible via this resource Direct read access to read write file returns the defining values Table 156 Read write file defining values Defining value Offset Value RID 13...

Page 128: ...er PC_BUFFER0 PC_BUFFER1 PC_BUFFER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_OFF_H PC_OFF_L PC_CTRL Write 11 22 33 44 55 66 77 88 3D 31 00 33 01 Wait for FREL 1 Read 8 10 3 File status This resource returns the status of the currently loaded file see chapter 8 10 1 Direct read access to file status returns the defining values Table 160 File status defining values...

Page 129: ...ER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_OFF_H PC_OFF_L PC_CTRL Write 59 32 00 00 01 Wait for FREL 1 Read 20 00 Buff er2 00h Buff er3 35h 8 10 4 Create delete change file This resource is used for the creation changing or deletion of a user file Direct read access to create delete change file returns the defining values Table 163 Create delete change file def...

Page 130: ... a file Table 165 Offset value for creating a file Bits Value Definition 14 10 Reserved for later use 9 8 11b Create file 7 4 Write access rights 0 Public 1 Operator 2 Maintenance 3 Authorized client 4 Service 5 14 Reserved for later use 15 No write operation permitted 3 0 Read access rights 0 Public 1 Operator 2 Maintenance 3 Authorized client 4 Service 5 14 Reserved for later use 15 No read oper...

Page 131: ...tion of a file with the name FILE1 read access 0 write access 1 Transaction Register PC_BUFFER0 PC_BUFFER1 PC_BUFFER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_OFF_H PC_OFF_L PC_CTRL Write F I L E 1 00 00 00 3D 33 03 10 01 Wait for FREL 1 8 10 5 Directory When this resource is accessed a list of the existing user files is returned Direct read access to directory r...

Page 132: ...fol lows Table 172 Definition of directory directory basic data Byte Value Description 7 6 Reserved for later use 5 4 0 65535 Number of filled bytes in the user store 3 2 0 65535 Number of empty bytes in the user store 1 Reserved for later use 0 0 255 Number of user files The data from the user files offset 00h is returned in the long message buffer as follows Table 173 Definition of directory dat...

Page 133: ...ensors SensorHub components are nor mally customer specific and are developed in collaboration with SICK The following figures give block diagrams for these scenarios a Simple I Os MFB system Winding temperature NTC PTC b Extended Sensors Acceleration sHub MFB system Winding temperature sensors Figure 33 sHub categories 8 11 1 Access simple I Os This resource enables access to simple I Os connecte...

Page 134: ...fied in the product data sheet Table 178 Offset value for access simple I Os Offset value Description 0 to 127 I O number Table 179 Simple access I Os here Set digital output with I O number 0 Transaction Register PC_BUFFER0 PC_BUFFER1 PC_BUFFER2 PC_BUFFER3 PC_BUFFER4 PC_BUFFER5 PC_BUFFER6 PC_BUFFER7 PC_ADD_H PC_ADD_L PC_OFF_H PC_OFF_L PC_CTRL Write 00 00 00 01 00 00 00 00 3A 00 00 00 01 Wait for ...

Page 135: ... measurement will be calculated with a weighting of 50 50 against previous measurements 1 indicates that each new measurement will be calculated with a weighting of 1 against previous measurements The values for the input filter functions are determined as follows Table 182 Definition of manage simple I Os input filter Byte Value Description 0 0 1 to 100 101 to 255 Reserved Filter characteristics ...

Page 136: ...l characteristics in table 185 DSL Core top level Safety variant only parameter RX CRC checker interrupt controller main function registers secondary registers SYNC DSL OUT DSL enable Protocol Manager 2 Safe 2 Interface interrupt Events SPI PIPE CRC checker Safe 1 interface pipeline CRC checker integrator estimator DSL IN parameter TX sync generator framer sampler sequencer protocol manager fast_p...

Page 137: ...ition value availability Digital output dev_thr_err Indicator position estimator deviation threshold crossed Digital input bigend Byte sequence selection for register addresses Test signals Digital output estimator_on Indicator for active position estimator Digital output safe_channel_err Indicator for safety frame transmission errors Digital output safe_pos_err Indicator for safe position update ...

Page 138: ...YNC signal 0 04 µs The SYNC signal must be inactive for at least 0 04 µs per cycle SYNC signal jitter 26 ns 2 System clock cycles Characteristics of the SPI PIPE interface Clock of SPI PIPE 10 MHz Characteristics of the parameter channel Theoretical transmission rate 166 334 kBd Duration of access to the communications resource 167 1 100 µs short message Duration of access to the encoder resource ...

Page 139: ...r signal Max estimated position deviation spipipe_ss Input Selection SensorHub SPI spipipe_clk Input Clock for SensorHub SPI spipipe_miso Output SensorHub SPI master input data slave output data dsl_in Input DSL link input data dsl_out Output DSL link output data dsl_en Output DSL link transceiver activation 9 1 Interface blocks Various interface blocks for the IP Core allow simpler access for dif...

Page 140: ...rface blocks 9 2 Serial interface block As an example a serial interface block is supplied together with the IP Core In this example a Full Duplex Serial Peripheral Interface SPI is installed The figure and table below show the interface signals Serial Interface SPI clk rst spi_miso spi_mosi spi_clk spi_sel bit_period 0 2 online_status_d 0 15 hostd_a 0 6 hostd_di 0 7 hostd_do 0 7 hostd_r hostd_w h...

Page 141: ...188 SPI interface characteristics Parameter Value Units Comments Mini mum Typical Maxi mum Clock spi_clk 10 MHz Clock phase PHA PHA 1 scanning during falling clock edge Clock polarity POL POL 0 base value of the clock is 0 Data endianness MSB is clocked out first The SPI interface block implements the following register based transactions Read individual register Read several registers with random...

Page 142: ...k high 25 60 ns h Delay spi_miso at spi_sel low 25 60 ns i Time for spi_sel low 50 ns 9 2 2 Dummy read process Due to the transmission of the online status Online Status read transactions need less time for transmission via spi_mosi than when receiving via spi_miso Therefore when receiving via spi_miso dummy read transactions must be inserted into spi_mosi to avoid unwanted extra transactions A re...

Page 143: ... ADDR 9 2 5 Write to individual register Using the SPI transaction Write to individual register an individual register can be writ ten to in the IP Core of the DSL Master Symbol Meaning W Access bit Write 0 REG ADDR Register address 00h to 7Fh REG DATA Register content ONLINE STATUS H Online status High byte ONLINE STATUS L Online status Low byte spi_ss spi_clk spi_mosi spi_miso W REG ADDR ONLINE ...

Page 144: ...us is not transmitted twice NOTE The write operation must always form the final part of the Read write sequence Multi ple and single read or write accesses cannot be combined Symbol Meaning R Access bit Read 1 W Access bit Write 0 REG ADDR 1 Register address for read access 00h to 7Fh REG ADDR 2 Register start address for write access 00h to 7Fh REG DATA 2 Register content for write access MASTER ...

Page 145: ...st dsl_a 0 5 dsl_di 0 15 dsl_do 0 15 dsl_ce_l bit_period 0 2 hostd_a 0 6 hostd_di 0 7 hostd_do 0 7 hostd_r hostd_w hostd_f User interface IP Core interface dsl_oe_l dsl_we_l dsl_wait dsl_freeze dsl_8n16 bigend dsl_ba dsl_be 0 1 Figure 38 Parallel interface block signals NOTE Please note that the EMIFA block supplied with the HIPERFACE DSL IPCore is only fit for the usage with drive interface It ca...

Page 146: ...t Data bus core to interface hostd_r output Read access requirement hostd_w output Write access requirement hostd_f output Freeze register selection Should be set 1 cycle before reading starts NOTE Note that the parallel interface does not implement the online_status signals These signals must be recorded by the user separately to the parallel interface The signal characteristics of the parallel i...

Page 147: ...IFA interface dsl_ce_l Slave parallel bus selection This signal can be an internally generated selection signal chip enable or part of the address decoding If this sig nal is deactivated 1 no access to the DSL Master is possible dsl_oe_l Input Output switch on This signal gives the time control for a direction switch of the bi directional bus dsl_we_l Input Switch on write access This signal gives...

Page 148: ...s 4 2 top level output 9 4 1 General information The main signals for accessing the basic interface are the address bus hostd_a the data in hostd_di and data out hostd_do lines as well as their respective read and write flags hostd_r and hostd_w Apart from these access signals there are two other important signals 1 The register freeze flag hostd_f This flag controls the updating of multi byte reg...

Page 149: ... long as the address is not changed This is the fastest reading procedure possible for the IP Core 9 4 3 Write access timing The write access through the basic interface must be implemented according to the diagram below 110 111 101 100 000 001 011 110 110 111 100 101 000 bit_period hostd_w hostd_a hostd_di register address data to write Figure 41 Write access basic interface For write operations ...

Page 150: ...l bus register address assignment Signal Register address dsl_a 5 0 Bit 6 1 dsl_ba Bit 0 The table below specifies the relevant address assignment Table 197 Address assignment for the DSL Master Designation 8 bit Big Endian 8 bit Little Endian 16 bit Big Endian 16 bit Little Endian SYS_CTRL 00h 03h 00h 15 8 02h 15 8 SYNC_CTRL 01h 02h 00h 7 0 02h 7 0 MASTER_QM 03h 00h 02h 7 0 00h 7 0 EVENT_H 04h 07...

Page 151: ... 7 0 28h 7 0 PC_CTRL 2Ch 2Dh 2Ch 15 8 2Ch 15 8 PIPE_S 2Dh 2Fh 2Ch 7 0 2Eh 15 8 PIPE_D 2Eh 2Eh 2Eh 15 8 2Eh 7 0 PC_DATA 2Fh 2Ch 2Eh 7 0 2Ch 7 0 ACC_ERR_CNT 38h 38h 38h 15 8 38h 7 0 MAXACC 39h 39h 38h 7 0 38h 15 8 MAXDEV_H 3Ah 3Bh 3Ah 15 8 3Ah 15 8 MAXDEV_L 3Bh 3Ah 3Ah 7 0 3Ah 7 0 DUMMY 3Fh 3Fh n v n v 9 6 Implementation of the IP Core for Xilinx Spartan 3E 6 The DSL Master IP Core is provided by SI...

Page 152: ...ompanying CD ROM All IP Cores with all interface blocks are packaged as ZIP files that can be found on the accompanying CD ROM in the IP Core Xilinx folder Table 200 IP Core Xilinx Spartan 3E 6 Zip file yymmdd dslmaster_ xilinx zip yymmdd defines the release date of the IP Core in the format year yy month mm and day dd 9 6 2 Design resources The DSL Master IP Core is supplied as a net list in NGC ...

Page 153: ...nt is black_box begin component_name dslm_n port map In Verilog this instantiation is in accordance with the following template module dslm_n endmodule dslm_n module_name synthesis attribute box_typeofdslm_n is black_box 9 6 3 Demo project To get started quickly each IP Core is supplied with a demo project for Xilinx ISE This demo project contains all the settings to begin the installation of the ...

Page 154: ...er_n_bus xise wrapper_n_spi xise x x Xilinx ISE project file Spartan 3E ISE_sp6 wrapper_n_bus xise wrapper_n_spi xise x x Xilinx ISE project file Spartan 6 Sequence of the demo project This chapter lists the steps that are required to carry out the demo project for the Stan dard variant with SPI interface in Xilinx ISE 12 1 Start ISE Project Navigator Open the Standard project file 9 FPGA IP CORE ...

Page 155: ...E Project Navigator should appear as follows Start the circuit synthesis FPGA IP CORE 9 8017595 ZTW6 2018 01 15 SICK T E C H N I C A L I N F O R M A T I O N HIPERFACE DSL 155 Subject to change without notice ...

Page 156: ...ided by SICK for Altera FPGA components The IP Core is available in the form of encrypted VHDL files These can be used for synthesis on all Altera FPGAs of sufficient size 9 FPGA IP CORE 156 T E C H N I C A L I N F O R M A T I O N HIPERFACE DSL 8017595 ZTW6 2018 01 15 SICK Subject to change without notice ...

Page 157: ...ety functions and diag nostics in accordance with the requirements which are described in this manual and which are required for specific motor feedback systems see the corresponding data sheet Both variants can be combined with various interface blocks see chapter 9 1 Exam ple projects are provided on the accompanying CD ROM All IP Cores with interface blocks are packaged in a ZIP file and can be...

Page 158: ..._master_pm vhd e_par_mrx vhd e_par_mtx vhd e_par_pm vhd e_pipeline vhd e_reset_sync vhd e_sampler vhd e_sequencer vhd e_sync_gen vhd x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Encrypted VHDL modules source Exter nal_Blocks spi_ctrl vhd bus_ctrl vhd x x Open VHDL modules license DSL_encr_license dat x x License file for use of the encrypted VHDL ...

Page 159: ...talled In the Tools menu in Quartus II click on the License Setup entry The Options dia log box is displayed Under the entry License file select the associated license file FPGA IP CORE 9 8017595 ZTW6 2018 01 15 SICK T E C H N I C A L I N F O R M A T I O N HIPERFACE DSL 159 Subject to change without notice ...

Page 160: ...9 FPGA IP CORE 160 T E C H N I C A L I N F O R M A T I O N HIPERFACE DSL 8017595 ZTW6 2018 01 15 SICK Subject to change without notice ...

Page 161: ...ially for power supply and grounding conditions but not limited to them Within Whitepaper Doc 8018857 information are provided about potential subjects which need to be considered and checked for a successful installation 10 1 Servo controller recommendations The servo controller part within the system configuration contains software routines as well as hardware design and components for interface...

Page 162: ... available resources of each encoder family please refer to the according product information document At the initial start up of the system the servo controller needs to read out the actual encoder configura tion to identify available encoder functionality see also chapter 10 1 5 10 1 5 Encoder identification Encoders can have different configurations resolution single multi turn motor temper atu...

Page 163: ...red that this ground connection has a low impedance to the controller ground connection and further It needs to be assured that EMC noise is well drained and not bounced back into the cable For installation grounding condition please refer also to chapter 10 4 10 1 9 Verification To check and verify the successful integration of the HDSL technology into the servo controller different tests can be ...

Page 164: ... tions of the manufacturer 10 2 2 Encoder connection set With the encoder connecting set the encoder is connected to the motor connector inside the motor SICK provides this configured cable set as an accessory Here the wires are already assembled to the connector for the HDSL connection to the encoder For the connection between the encoder to the motor connector the length shall be minimized witho...

Page 165: ...ontroller needs particular information about the connected motor For interchangeable configurations different motors brands at a controller a default set of data is stored at the encoder within an electronic motor type label The use of additional manufacturer specific data files is not limited by this requirement Within an electronic motor type label the following data could be listed extracted fr...

Page 166: ... the system configuration contains the cable between the servo controller connection point and the motor connector as well as potential cou plings within the line 10 3 1 Cable The combination of data lines and motor power lines within one cable is done with the so called hybrid cable type Herein the data lines are protected against electromagnet icdisturbances by different measures as good as poss...

Page 167: ... particular connector follow the according instructions of the manufacturer For interchangeable components motor cable the pin layout as shown at the figure below shall be used 9 pin M23 size motor connector Figure 43 Pin layout M23 Pin layout for a M23 size motor connector Main brake line shielding is connected together to the connector housing within the connector also PE is connected to the con...

Page 168: ...needs In such cases the differences need to be assessed and the HDSL system config uration can be adjusted to particular requirements The two important external impacts to the HDSL system performance are The power supply and grounding conditions Application changes and field modifications 10 4 1 Power supply and grounding conditions Most power supply ratings for current HDSL servo motor applicatio...

Page 169: ...42 143 143 144 144 146 P Parallel bus 30 136 136 140 147 150 Parameter data 8 69 Parameters Channel 13 14 23 29 33 34 38 40 48 50 51 53 67 67 68 72 Pin functions 19 21 138 138 Position data 9 19 22 37 73 Process data 8 11 11 12 27 29 35 45 61 104 105 Protocol package 9 10 11 12 12 14 35 Q Quality monitoring 32 32 35 37 40 60 61 84 R Recommend fault handling 84 Resolution 19 54 55 63 94 110 138 S S...

Page 170: ... for polling parameter data of an encoder that must first be processed by the encoder Motor feedback sys tem Rotary or linear encoder for use in servo drives RS485 Radio Sector Standard 485 also designated as EIA 485 or TIA 485 A standard for ser ial data transmission over symmetric pair cables RSSI Received Signal Strength Indicator SensorHub Interface between a motor feedback system and an exter...

Page 171: ...n function to reset user file system Addition and clarification of functions in regard to new DSL prod ucts EFx50 and EEx37 LED current position filter 6 6 2016 03 Update to DSL Master version 1 07 Bugfix related Test messages and POSTX signals Addition of RELEASE register Addition of interface circuit design recommendation Adjustments of resources and errors for different encoder types EKx EFx EE...

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