10-3. Pin description
10-3-1. CPU Direct/VL-Bus Interface
Pin names in parentheses (...) indicate alternate functions.
Pin#
Pin Name
Type
Active
Description
207
RESET
In
Low
Reset. For VL-Bus interfaces, connect to RESET#. For direct CPU local bus
interfaces, connect to the system reset generated by the motherboard system logic
for all peripherals (not the RESET# pin of the processor). This input is ignored
during Standby mode (STNDBY# pin low) so that the remainder of the system (and
the system bus) may be safely powered down during Standby mode if desired.
22
ADS#
In
Low
Address Strobe. In VL-Bus and CPU local bus interfaces ADS# indicates valid
address and control signal information is present. It is used for all decodes and to
indicate the start of a bus cycle.
31
M/IO#
In
Both
Memory / IO. In VL-Bus and CPU local bus interfaces M/IO# indicates either a
memory or an I/O cycle:
1 = memory, 0 = I/O.
11
W/R#
In
Both
Write / Read. This control signal indicates a write (high) or read (low) operation. It
is sampled on the rising edge of the (internal) 1x CPU clock when ADS# is active.
23
RDYRTN# for 1x Clock
config
CRESET for 2X clock config
In
Low
High
Ready Return. Handshaking signal in VL-Bus interface indicating synchronization
of RDY# by the local bus master / controller to the processor. Upon receipt of this
LCLK-synchronous signal the chip will stop driving the bus (if a read cycle was
active) and terminate the current cycle.
24
LRDY#
Out/OC
Low
Local Ready. Driven low during VL-Bus and CPU local bus cycles to indicate the
current cycle should be completed. This signal is driven high at the end of the
cycle, then tri-stated. This pin is tri-stated during Standby mode (as are all other
bus interface outputs).
25
LDEV#
Out
Low
Local Device. In VL-Bus and CPU local bus interfaces, this pin indicates that the
chip owns the current cycle based on the memory or I/O address which has been
broadcast. For VL-Bus, it is a direct output reflecting a straight address decode.
This pin is tri-stated during Standby mode (as are all other bus interface outputs).
27
LCLK
In
Both
Local Clock. In VL-Bus this pin is connected to the CPU 1x clock. In CPU local bus
interfaces it is connected to the CPU 1x or 2x clock. If the input is a 2x clock, the
processor reset signal must be connected to CRESET (pin 23) for synchronization
of the clock phase.
43
BE0# (BLE#)
In
Low
Byte Enable 0. Indicates data transfer on D7:D0 for the current cycle.
32
BE1#
In
Low
Byte Enable 1. Indicates data transfer on D15:D8 for the current cycle.
21
BE2#
In
Low
Byte Enable 2. Indicates data transfer on D23:D16 for the current cycle.
10
BE3#
In
Low
Byte Enable 3. BE3# indicates that data will transfer over the data bus on D31:24
during the current access.
179
A2
In
High
System Address Bus. In VL-Bus, and direct CPU interfaces, the address pins are
connected directly to the bus. In internal clock synthesizer test mode (TS# = 0 at
Reset), A24 becomes VCLK out and A25 becomes MCLK out. A26 and A27 may
be alternately be used as General Purpose I/O pins or as Activity Indicator and
Enable Backlight respectively (see panel interface pin descriptions and FR0F and
FR0C for more details). If A26 and A27 are used as GPIO pins, they may be
programmed as a 2-pin CRT Monitor DDC interface (VESA
Ô
"Display Data
Channel" also referred to as the "Monitor Plug-n-Play" interface). Either A26 or A27
may also be used to output Composite Sync for support of an external NTSC / PAL
encoder chip.
180
A3
In
High
182
A4
In
High
183
A5
In
High
185
A6
In
High
186
A7
In
High
187
A8
In
High
188
A9
In
High
189
A10
In
High
190
A11
In
High
191
A12
In
High
192
A13
In
High
193
A14
In
High
194
A15
In
High
195
A16
In
High
196
A17
In
High
197
A18
In
High
198
A19
In
High
199
A20
In
High
200
A21
In
High
201
A22
In
High
28
A23
In
High
29
A24
In
High
30
A25
In
High
53
A26
In
High
54
A27
In
High
5 – 31
Summary of Contents for UP-5700
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Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...
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