10-3-2. PCI Bus Interface
Pin#
Pin Name
Type
Active
Description
207
RESET#
In
Low
Reset. This input sets all signals and registers in the chip to a known state.
All outputs from the chip are tri-stated or driven to an inactive state. This pin
is ignored during Standby mode (STANDBY# pin low). The remainder of the
system (therefore the system bus) may be powered down if desired (all bus
output pins are tri-stated in Standby mode).
201
CLK
In
High
Bus Clock. This input provides the timing reference for all bus transactions.
All bus inputs except RESET# and INTA# are sampled on the rising edge of
CLK. CLK may be any frequency from DC to 33MHz.
31
PAR
I/O
High
Parity. This signal is used to maintain even parity across AD0-31 and C/BE0-
3#. PAR is stable and valid one clock after the address phase. For data
phases PAR is stable and valid one clock after either IRDY# is asserted on
a write transaction or TRDY# is asserted on a read transaction. Once PAR
is valid, it remains valid until one clock after the completion of the current
data phase (i.e., PAR has the same timing as AD0-31 but delayed by one
clock). The bus master drives PAR for address and write data phases; the
target drives PAR for read data phases.
22
FRAME#
In
Low
Cycle Frame. Driven by the current master to indicate the beginning and
duration of an access. Assertion indicates a bus transaction is beginning
(while asserted, data transfers continue); de-assertion indicates the
transaction is in the final data phase
23
IRDY#
In
Low
Initiator Ready. Indicates the bus master’s ability to complete the current
data phase of the transaction. During a write, IRDY# indicates valid data is
present on AD0-31; during a read it indicates the master is prepared to
accept data. A data phase is completed on any clock when both IRDY# and
TRDY# are sampled then asserted (wait cycles are inserted until this
occurs).
24
TRDY#
S/TS
Low
Target Ready. Indicates the target’s ability to complete the current data
phase of the transaction. During a read, TRDY# indicates that valid data is
present on AD0-31; during a write it indicates the target is prepared to
accept data. A data phase is completed on any clock when both IRDY# and
TRDY# are sampled then asserted (wait cycles are inserted until this
occurs).
27
STOP#
S/TS
Low
Stop. Indicates the current target is requesting the master to stop the
current transaction.
25
DEVSEL#
S/TS
Low
Device Select. Indicates the current target has decoded its address as the
target of the current access
29
PERR# (VCLKOUT)
S/TS
Low
Parity Error. This signal reports data parity errors (except for Special Cycles
where SERR# is used). The PERR# pin is Sustained Tri-state. The
receiving agent will drive PERR# active two clocks after detecting a data
parity error. PERR# will be driven high for one clock before being tri-stated
as with all sustained tri-state signals. PERR# will not report status until the
chip has claimed the access by asserting DEVSEL# and completing the
data phase.
30
SERR# (MCLKOUT)
OD
Low
System Error. Used to report system errors where the result will be
catastrophic (address parity error, data parity errors for Special Cycle
commands, etc.). This output is actively driven for a single PCI clock cycle
synchronous to CLK and meets the same setup and hold time requirements
as all other bused signals. SERR# is not driven high by the chip after being
asserted, but is pulled high only by a weak pull-up provided by the system.
Thus, SERR# on the PCI Bus may take two or three clock periods to fully
return to an inactive state.
5 – 33
Summary of Contents for UP-5700
Page 139: ...1 UP 5700 Main PWB CHAPTER 10 PWB LAYOUT A side 10 1 ...
Page 140: ...2 UP 5700 CPU PWB A side UP 5700 CPU PWB B side 10 2 ...
Page 141: ...3 UP 5700 KEY I F PWB A side CN2 UP 5700 KEY I F PWB B side 10 3 ...
Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...
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