![background image](http://html.mh-extra.com/html/sharp/up-5700/up-5700_service-manual_373332072.webp)
Pin#
Pin Name
Type
Active
Description
43
C/BE0#
In
Low
Bus Command / Byte Enables. During the address phase of a bus
transaction, these pins define the bus command (see list above). During the
data phase, these pins are byte enables that determine which byte lanes
carry meaningful data:
byte 0 corresponds to AD0-7,
byte 1 corresponds to 8-15,
byte 2 corresponds to 16-23,
byte 3 corresponds to 24-31.
32
C/BE1#
In
Low
21
C/BE2#
In
Low
10
C/BE3#
In
Low
11
IDSEL
In
High
Initialization Device Select. Used as a chip select during configuration read
and write transactions
145
AA0 (LB#)
(CFG0)
I/O
Low
Address bus for DRAMs A and B
See the configuration table in the Extended Register description section for
complete details on the configuration options for CFG0-8 (XR70-71). See
MAD2-7 (pins 164-169) and XR71 for additional configuration inputs
(CFG10-15).
Since the 65550 does not support the "internal oscillator" option, pin CFG5
(AA5) must be pulled down on reset.
146
AA1 (Reserved) (CFG1)
I/O
High
147
AA2 (2X#)
(CFG2)
I/O
High
148
AA3 (Reserved) (CFG3)
I/O
High
149
AA4 (Reserved) (CFG4)
I/O
High
150
AA5 (OS#)
(CFG5)
I/O
High
151
AA6 (AD#)
(CFG6)
I/O
High
152
AA7 (TS#)
(CFG7)
I/O
High
153
AA8 (LV#)
(CFG8)
I/O
High
90
CA0 (P16)
Out
High
Address bus for DRAM C
91
CA1 (P17)
Out
High
92
CA2 (P18)
Out
High
93
CA3 (P19)
Out
High
94
CA4 (P20)
Out
High
95
CA5 (P21)
Out
High
96
CA6 (P22)
Out
High
97
CA7 (P23)
Out
High
98
CA8 (BLANK)
I/O
Hi/Lo
CA8 may be configured as VAFC BLANK# out or vertical reference input
(VREF) for video capture.
99
HREF
In
High
Horizontal reference input for video capture.
156
RASA#
(RASAB0#)
Out
Low
RAS for DRAM A (or bank 0 in 2MB configurations)
123
RASB#
(RASAB1#)
Out
Low
RAS for DRAM B (or bank 1 in 2MB configurations)
101
RASC#
(VRDY)
Out
Low
RAS for DRAM C or color key input from external PC-Video source (or
VAFC "Video System Ready" input)
(KEY)
In
High
160
CASAL#
(WEAL#)
Out
Low
CAS for the DRAM A lower byte
159
CASAH#
(CASA#)
Out
Low
CAS for the DRAM A upper byte
126
CASBL#
(WEBL#)
Out
Low
CAS for the DRAM B lower byte
125
CASBH#
(CASB#)
Out
Low
CAS for the DRAM B upper byte
104
CASCL#
(WECL#)
I/O
Both
DRAM C low byte CAS, video in red-6 or VAFC VP14
(VR6/VP14)
103
CASCH#
(CASC#)
I/O
Both
DRAM C high byte CAS, video in red-7 or VAFC VP15
(VR7/VP15)
157
WEA#
(WEAH#)
Out
Low
Write enable for DRAM A (or bank 0 in 2MB)
(WEAB0#)
124
WEB#
(WEBH#)
Out
Low
Write enable for DRAM B (or bank 1 in 2MB)
(WEAB1#)
Out
High
102
WEC#
(WECH#)
Out
Both
Write enable for DRAM C or video in port PCLK out
(PCLK)
155
OEAB0#
Out
Low
Output enable for DRAMs A and B, bank 0, 1 of 2MB
100
OEC#
Out
Low
Output enable for DRAM C or VAFC "Video Input Clock" if DRAM C not used
(VCLK)
In
High
Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before released,
and are not driven for at least one cycle after being released by the previous device. A pull-up provided by the bus controller is used to
maintain an inactive level between transactions.
Low (= 0)
High (= 1)
AA0
PCI Bus
VL-Bus
AA2
2x Clock
1x Clock
AA5
Ext. Clock (14.3 Mhz)
Not supported
AA6
A26-A27
ENABKL/ACTI
AA7
Clock Test Mode
Clock Test mode disable
AA8
IVcc/CVcc = 3.3V
IVcc/Cvcc = 5.0V
5 – 35
Summary of Contents for UP-5700
Page 139: ...1 UP 5700 Main PWB CHAPTER 10 PWB LAYOUT A side 10 1 ...
Page 140: ...2 UP 5700 CPU PWB A side UP 5700 CPU PWB B side 10 2 ...
Page 141: ...3 UP 5700 KEY I F PWB A side CN2 UP 5700 KEY I F PWB B side 10 3 ...
Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...
Page 145: ...7 2 Sub PWB Side A Side B 10 7 ...