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Signal Name
Pin No.
Signal Type
(Drive)
Selected By
Signal Description
DACKC#/DACK2#
K24
O
Programmable DMA Acknowledge C/DACK2#: DACK# is used to
acknowledge DRQ to allow DMA transfer.
This input defaults to DACK2#, however, it can be programmed to
route onto any internal DACK# by programming PCIDV1 C1h[2:0].
PPWR6
PCIDV1
C1h[2:0] = 100
Peripheral power control Line 6
DACKD#/DACK3#
K25
O
Programmable DMA Acknowledge D/DACK3#: DACK# is used to
acknowledge DRQ to allow DMA transfer.
This input defaults to DACK3#, however, it can be programmed to
route onto any internal DACK# by programming PCIDV1 C1h[6:4].
PPWR7
PCIDV1
C1h[6:4] = 100
Peripheral power control Line 7
DACKE#/DACK5#
K26
O
Programmable DMA Acknowledge E/DACK5#: DACK# is used to
acknowledge DRQ to allow DMA transfer.
This input defaults to DACK5#, however, it can be programmed to
route onto any internal DACK# by programming PCIDV1 C2h[6:4].
PPWR13
PCIDV1
C2h[6:4] = 100
Peripheral power control Line 13
DACKE#/DACK6#
J22
O
Programmable DMA Acknowledge F/DACK6#: DACK# is used to
acknowledge DRQ to allow DMA transfer.
This input defaults to DACK6#, however, it can be programmed to
route onto any internal DACK# by programming PCIDV1 C3h[2:0].
PPWR14
PCIDV1
C3h[2:0] = 100
Peripheral power control Line 14
DACKG#/DACK7#
J23
O
Programmable DMA Acknowledge G/DACK7#: DACK# is used to
acknowledge DRQ to allow DMA transfer.
This input defaults to DACK7#, however, it can be programmed to
route onto any internal DACK# by programming PCIDV1 C3h[6:4].
PPWR15
PCIDV1
C3h[6:4] = 100
Peripheral power control Line 15
Compact ISA Interface
RSTDRV
AC25
I/O
(4mA)
PCIDV1
8Fh = 00h
Reset Drive: Active high reset signal to ISA bus devices.
RSTDRV can be programmed to toggle in Suspend via SYSCFG
40h[0].
PIO15
PCIDV1
8Fh
¹
00h
Programmable Input/Output 15: See Section 3.3, "Programmable
I/O Pins", on page 33 for more details.
SD[15:0]
Refer to
Table 3-2
I/O
(8nA)
Cycle
Multiplexed
System Data Bus: SD[15:0] provides the 16-bit data path for devices
residing on the ISA bus.
MAD[15:0]
Multiplexed Address/Data Bus: Used during CISA cycles.
SEL/ATB#
AC20
I/O
(4mA)
PCIDV1
8Eh = 00h
Select Back-off: Dedicated CISA input.
This signal needs to be pulled up externally.
SDCKE
PCIDV1
53h[3] = 1
SDRAM Clock Enable: This signal is asserted to put the SDRAM
into a "Stop" state. The BIOS can program FireStar to assert this
signal only in Suspend mode.
PIO14
PCIDV1
8Eh
¹
00h
Programmable Input/Output 14: See Section 3.3, "Programmable
I/O Pins", on page 33 for more details.
CMD#
AB20
O
(4mA)
SYSCFG
16h[7, 5]
Command: Dedicated CISA output used to signal a data transfer
command.
DIRTY
I/O
(4mA)
Tag Dirty Bit: This dirty bit allows the tag data to be 8 bit wide
instead of 7.
PCICLK3
O
(4mA)
ROMCS#:
KBDCS# strap
option
PCI Clock Output 3
5 – 22
Summary of Contents for UP-5700
Page 139: ...1 UP 5700 Main PWB CHAPTER 10 PWB LAYOUT A side 10 1 ...
Page 140: ...2 UP 5700 CPU PWB A side UP 5700 CPU PWB B side 10 2 ...
Page 141: ...3 UP 5700 KEY I F PWB A side CN2 UP 5700 KEY I F PWB B side 10 3 ...
Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...
Page 145: ...7 2 Sub PWB Side A Side B 10 7 ...