Name
Number
Type
Description
WRTPRTJ
14
IS
Write Protected. This active-low Schmitt Trigger input senses from the disk drive that a disk is write-
protected. Any write command is ignored.
TRK0J
13
IS
Track 00. This active low Schmitt Trigger input senses from the disk drive that the head is positioned
over the outermost track.
INDEXJ
12
IS
Index. This active low Schmitt Trigger input senses form the disk drive that the head is positioned over
the beginning of a track, as marked by an index hole.
UR1IRQB
18
O24
Serial Port Interrupt Request. Alternate IRQ output from UART1, refer to CR0 bit 6.
NCSJ
DRATE0
19
I
O24
NCSJ. This pin is used as an input for an external decoder circuit which is used to qualify address lines
above all. If this pin is logically ORed with A11-A15, then it can qualify as 16-bit full decoder. If this
function is not used, this pin must be connected to ground.
As an output function, this pin reflects the bit 0 of the data rate register.
Serial Port Interface
RXD1,
RXD2
78, 88
I
Receive Data. Receiver serial data input.
TXD1,
PCF0
79
O4
I
Transmit Data. Transmitter serial data output from Primary Serial Port.
Parallel Port configuration control 0. During reset active, this input signal is read and latched to
define the address of the Parallel port.
RTS1J
RCF1
81
O4
I
Request to send. Active low Request to send output for Primary Serial port. Handshake output signal
notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to
bit 1 of Modem Control Register (MCR). The hardware reset will clear the RTSJ signal to inactive mode
(high). Forced inactive during loop mode operation.
Parallel port configuration control 1. During reset active, this input is read and latched to define the
address of the Parallel port.
RTS2J
S2CF0
91
O4
I
Request to send. This active low output for Secondary Serial Port. Handshake output signal notifies
modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of
Modem Control Register (MCR). The hardware reset will clear the RTSJ signal to inactive mode (high).
Forced inactive during loop mode operation.
Secondary serial port configuration control 0. During reset active, this input is read and latched to
define the address of the Secondary serial port.
DTR1J
ECPEN0
83
O4
I
Data Terminal Ready. This is an active low output for primary serial port. Handshake output signal
signifies modem that the UART is ready to establish data communication link. This signal can be
programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the
DTRJ signal to inactive during loop mode operation.
Enhanced parallel port mode seject. Read and latched during reset active.
DTR2J
S2CF1
93
O4
I
Data Terminal Ready. This active low output is for secondary serial port. Handshake output signal
notifies modem that the UART is ready to establish data communication link. This signal can be
programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the
DTRJ signal to inactive mode (high). Forced inactive during loop mode operation.
Secondary serial port configuration control 1. When active, this input is read and latched to define
the address of the Secondary Serial port.
FXD2
FDCCF
89
O4
I
Transmitter Serial Data output from Secondary Serial Port.
Floppy Disk Configuration. This input is read and latched during Reset to enable/disable the Floppy
Disk Controller.
CTS1J
CTS2J
82, 92
I
Clear to Send. This active low input for primary and secondary serial ports. Handshake signal which
notifies the UART that the modem is ready to receive data. The CPU can monitor the status of CTSJ
signal by reading bit 4 Modem status Register (MSR). A CTSJ signal state change from low to high
after the last MSR read will set MSR bit 0 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt
is generated when CTSJ changes state. The CTSJ signal has no effect on the transmitter. Note: Bit 4 of
MSR is the complement of CTSJ.
DSR1J
DSR2J
80, 90
I
Data Set Ready. This active low input is for primary and secondary serial ports. Handshake signal
which notifies the UART that the modem is ready to establish the communication link. The CPU can
monitor the status of DSRJ signal by reading bit 5 of Modem Status Register (MSR). A DSRJ signal
state changes from low to high after the last MSR read sets MSR bit 1 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated when DSRJ changes state.
Note: Bit 5 of MSR is the complement of DSRJ.
DCD1J,
DCD2J
85, 87
I
Data Carrier Detect. This active low input is for primary and secondary serial ports. Handshake signal
which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status
of DCDJ signal by reading bit 7 of Modem Status Register (MSR). A DCDJ signal state changes from
low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set,
the Interrupt is generated when DCDJ changes state. Note: bit 7 of MSR is the complement of DCDJ.
RI1J, RI2J
84, 86
I
Ring Indicator. This active low input is for primary and secondary serial ports. Handshake signal which
notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the
status of RIJ signal by reading bit 6 of Modem Status Register (MSR). An RIJ signal state change from,
low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when RIJ changes state. Note, bit 6 of MSR is the complement of RIJ.
5 – 41
Summary of Contents for UP-5700
Page 139: ...1 UP 5700 Main PWB CHAPTER 10 PWB LAYOUT A side 10 1 ...
Page 140: ...2 UP 5700 CPU PWB A side UP 5700 CPU PWB B side 10 2 ...
Page 141: ...3 UP 5700 KEY I F PWB A side CN2 UP 5700 KEY I F PWB B side 10 3 ...
Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...
Page 145: ...7 2 Sub PWB Side A Side B 10 7 ...