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20-2. Timing Chart
(A) Power cut:
SSR1 07F1h[1]=0 is set.
(B) Power off:
SSR1 07F1h[1]=0 is set.
Power supply is assured only for 50ms from the falling of ACL, setting
SSR1 07F1h[1]=0 must be performed within 50ms from the falling of
ACL. When this operation is not performed and the power supply is
active, the PSC2 sets SSR1 07F1h[1]=0 at 200ms after the falling of
ACL.
20-3. Control of Power ON/OFF and Register
Sensing State of AC SW
General purpose port (PSC+408h)=588h
HIOP
b7 b6
b5
b4
b3 b2
b1
b0
Read
0
0
PHOLD
SLEEP
0
0
PHSNS
MLOCK
Write
0
0
PHOLD
SLEEP
0
0
0
0
Bit 7-6:
Not used.
Bit 5:
AC power supply hold signal
PHOLD="0": Power is turned off when the AC switch is set OFF.
PHOLD="1": Power continues to be supplied even when the AC
switch is set OFF.
The initial value of PHOLD is "0". To prohibit power off by the manual
operation of the AC switch, set PHOLD to "1".
When not prohibiting power off by the manual operation of the AC
switch, set PHOLD to "0".
PHOLD is designed in order to protect power off by the manual
operation of the AC switch, so this signal is not effective for the stop
of power supply due to power cut etc.
Bit 4: SLEEP=0
Operation Mode The power fan turns and the
power source of LCD back
light is connected.
SLEEP=1 Sleep Mode The power fan stops and the power source of
LCD back light is disconnected.
Note:
UP-5700 must be always used under SLEEP=0.
Bit 3-2: Not used.
Bit 1: Register sensing the status of AC switch
PHSNS="0": The AC switch is turned OFF.
PHSNS="1": The AC switch is turned ON.
Bit 0: UP-5700 is not used (whether the CPU cooler motor is
locked or not is sensed).
(MLOCK=0: The motor is running.)
(MLOCK=1: The motor is not running.)
20-4. Shutdown Control
The power switch of UP-5700 is used to switch the ON state and
stand-by state of terminal.
When starting up the terminal, the power switch is necessary to be
set ON. When the power switch is set to the position of stand-by
mode, the power source unit stops automatically. If HOP1 pin of the
PSC2 is held (PHOLD=1) by the software, the power source unit
continues to run until the software releases this holding.
If the software can not control shutdown, turning ON the shutdown
switch on the side panel can force stand-by mode to be released.
However, when the power switch is set ON, turning ON the shutdown
switch does not stop the power source unit.
21. Vacuum Fluorescent Display (VFD)
21-1. ER-A8DP
21-1-1. Outline
Content of display:
7 segments (7 digits
´
1 line) +
PSC2 internal CKDC I/F channel 2 is used.
21-1-2. ER-A8DP Control
The channel 2 of clock synchronous serial interface incorporated in
the PSC2 is used as previously defined CKDC interface. The I/O
address of this interface is PSC2+(012h-013h)=112h-113h.
21-2. UP-P20DP
21-2-1. Outline
Content of display: 5
´
7 dots (20 digits
´
2 lines) + comma
+
PSC2 internal UART4 is used as COM8.
(RS-232C level I/F, serial, 8 bits, non-parity, 1 stop-bit, 9600 bps, and
RXD/DSR/DTR)
When powering on, the mark blinks automatically.
21-2-2. UP-P20DP Control
The UART4 incorporated in the PSC2 as Mega Macro Function is
used. The I/O address of this interface is PSC2+(808h-80Fh)=988h-
98Fh.
21-2-3. Connector Specifications
RJ45
Pin No.
Signal
Function
I/O
1
+5V
+5V
—
2
ER
Data terminal Ready
O
3
SD
Send Data
O
4
SG
Signal Ground
—
5
SG
Signal Ground
—
6
(NC)
(Not Connected)
7
DR
Data set Ready
I
8
+5V
+5V
O
21-2-4. Cautions
ER-A8DP and UP-P20DP can not be used simultaneously with in-
stalled on the same system because of their power capacity.
PWGOOD
ACL
(200ms)
SDEN
300ms
RESET#
RSTDR
300ms
(A)
(A)
200ms
5 – 51
Summary of Contents for UP-5700
Page 139: ...1 UP 5700 Main PWB CHAPTER 10 PWB LAYOUT A side 10 1 ...
Page 140: ...2 UP 5700 CPU PWB A side UP 5700 CPU PWB B side 10 2 ...
Page 141: ...3 UP 5700 KEY I F PWB A side CN2 UP 5700 KEY I F PWB B side 10 3 ...
Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...
Page 145: ...7 2 Sub PWB Side A Side B 10 7 ...