10-3-5. CRT & Clock Interface
Pin#
Pin Name
Type
Active
Description
65
HYSNC (CSYNC)
OUT
Both
CRT Horizontal sync (polarity is programmable) or "Composite Sync" for support of
various external NTSC / PAL encoder chips. Note CSYNC can be set to output on the
ACTI or ENABKL pins.
64
VSYNC (VISINT)
OUT
Both
CRT Vertical Sync (polarity is programmable) or "VSync Interval" for support of various
external NTSC / PAL encoder chips.
60
RED
OUT
High
CRT analog video outputs from the internal color palette DAC. The DAC is designed for a
37.5
W
equivalent load on each pin (e.g. 75
W
resistor on the board, in parallel with the 75
W
CRT load).
58
GREEN
OUT
High
57
BLUE
OUT
High
55
RSET
In
N/A
Set point resistor for the internal color palette DAC. A 560
W
1% resistor is required
between RSET and AGND.
59
AVCC
VCC
—
Analog power and ground pins for noise isolation for the internal color palette DAC. AVCC
should be isolated from digital VCC as described in the Functional Description of the
internal color palette DAC. For proper DAC operation, AVCC should not be greater than
IVCC. AGND should be common with digital ground but must be tightly decoupled to
AVCC. See the Functional Description of the internal color palette DAC for further
information.
56
AGND
GND
—
203
XTALI (MCLK)
In
High
Crystal In. This pin serves as the input for an external reference oscillator (usually
14.31818 MHz). Note that in test mode for the internal clock synthesizer, MCLK is output
on A25 (pin 30) and VCLK is output on A24 (pin 29).
204
(Reserved)
Reserved. For compatibility with the 65545, this pin (formerly "Crystal Out" or "XTLAO")
must be disconnected. In addition, pin 150 must be pulled down on reset. The 65545 no
longer supports the "internal oscillator" option.
205
CVCC0
VCC
—
Analog power and ground pins for noise isolation for the internal clock synthesizer. Must
be the same as VCC for internal logic. VCC/GND pair 0 and VCC/GND pair 1 pins must
be carefully decoupled individually. Refer also to the section on clock ground layout in the
Functional Description. Note that the CVCC voltage must be the same as the voltage for
the internal logic (IVCC).
202
CGND0
GND
—
206
CVCC1
VCC
—
208
CGND1
GND
—
154
32KHz (GPIO2) (AA9)
In
High
Clock input for refresh of non-self-refresh DRAMs and panel power sequencing. This pin
can be programmed as GPIO2 instead of 32KHz input, or AA9 for 512Kx32 memory
configurations.
10-3-6. Power / Ground and Standby Control
Pin#
Pin Name
Type
Active
Description
178
STNDBY#
In
Low
Standby Control Pin. Pull this pin to place the chip in Standby Mode.
80
IVCC
VCC
—
Power / Ground (Internal Logic). 5V
±
10% or 3.3V
±
0.3V.
Note that this voltage must be the same as CVCC (voltage for internal clock synthesizer).
This voltage must also be equal to, or greater than, A VCC (voltage for DAC)
77
IGND
GND
—
181
IVCC
VCC
—
184
IGND
GND
—
9
BVCC
VCC
—
Power / Ground (Bus Interface). 5V
±
10% or 3.3V
±
0.3V.
12
BNGD
GND
—
26
BGND
GND
—
42
BVCC
VCC
—
39
BGND
GND
—
52
BGND
GND
—
66
DVCC
VCC
—
Power / Ground (Bus Interface). 5V
±
10% or 3.3V
±
0.3V.
63
DGND
GND
—
89
DGND
GND
—
158
MVCCA
Power / Ground (Bus Interface). 5V
±
10% or 3.3V
±
0.3V.
161
MGNDA
142
MVCCB
Power / Ground (Bus Interface). 5V
±
10% or 3.3V
±
0.3V.
139
MGNDB
108
MVCCC
Power / Ground (Bus Interface). 5V
±
10% or 3.3V
±
0.3V.
105
MGNDC
5 – 38
Summary of Contents for UP-5700
Page 139: ...1 UP 5700 Main PWB CHAPTER 10 PWB LAYOUT A side 10 1 ...
Page 140: ...2 UP 5700 CPU PWB A side UP 5700 CPU PWB B side 10 2 ...
Page 141: ...3 UP 5700 KEY I F PWB A side CN2 UP 5700 KEY I F PWB B side 10 3 ...
Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...
Page 145: ...7 2 Sub PWB Side A Side B 10 7 ...