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10-3-3. Display Memory Interface
Pin#
Pin Name
Type
Active
Description
162
MAD0 (TSENA#)
I/O
High
Memory data bus for DRAM A (lower 512KB of display memory)
MAD2-7 are latched into XR71 on reset for use as additional configuration inputs
(CFG10-12 are reserved by software for input of panel ID). These bits have no other
internal hardware configuration function.
PCI Bus: MAD8-15 are used as BIOS ROM Data inputs during system startup (i.e.,
before the system enables the graphics controller memory interface). See also pins
179-199 (in PCI Bus interface pin descriptions section) for BIOS ROM address and
ROM Chip Select outputs. In the VL-Bus mode, the BIOS ROM interface can be an
external circuit on the ISA Bus connector (see Application Schematics).
163
MAD1 (ICTENA#)
I/O
High
164
MAD2 (CFG10) EDO/FPM
I/O
High
165
MAD3 (CFG11) (PID0)
I/O
High
166
MAD4 (CFG12) (PID1)
I/O
High
167
MAD5 (CFG13) (PID2)
I/O
High
168
MAD6 (CFG14) (PID3)
I/O
High
169
MAD7 (CFG15) (Reserved)
I/O
High
170
MAD8 (PCI ROMD0)
I/O
High
171
MAD9 (PCI ROMD1)
I/O
High
172
MAD10 (PCI ROMD2)
I/O
High
173
MAD11 (PCI ROMD3)
I/O
High
174
MAD12 (PCI ROMD4)
I/O
High
175
MAD13 (PCI ROMD5)
I/O
High
176
MAD14 (PCI ROMD6)
I/O
High
177
MAD15 (PCI ROMD7)
I/O
High
127
MBD0
I/O
High
Memory data bus for DRAM B (upper 512KB)
128
MBD1
I/O
High
129
MBD2
I/O
High
130
MBD3
I/O
High
131
MBD4
I/O
High
132
MBD5
I/O
High
133
MBD6
I/O
High
134
MBD7
I/O
High
135
MBD8
I/O
High
136
MBD9
I/O
High
137
MBD10
I/O
High
138
MBD11
I/O
High
140
MBD12
I/O
High
141
MBD13
I/O
High
143
MBD14
I/O
High
144
MBD15
I/O
High
106
MCD0 (VB2) (EVID#)
I/O
High
Memory data bus for DRAM C (Frame Buffer)
When a frame buffer DRAM is not required, this bus may be used to input up to 18
bits of RGB data from an external PC-Video subsystem or 16 bits of RGB from an
external VAFC interface. Note that this configuration also provides additional panel
outputs so that a video input port may be implemented along with a 24-bit true-color
TFT panel (TFT panels never need DRAM C). In VAFC interface mode, pin 106 is
the VAFC "Enable Video" input. The external VAFC interface drives this pin low to
indicate data input on the VP0-15. EVID# is ignored (essertially reserved) in the
65550 (VAFC data is always expected as inputs). In VAFC mode, pin 119 is
"Graphics System Ready" out and is always driven high.
107
MCD1 (VB3) (VP0)
I/O
High
109
MCD2 (VB4) (VP1)
I/O
High
110
MCD3 (VB5) (VP2)
I/O
High
111
MCD4 (VB6) (VP3)
I/O
High
112
MCD5 (VB7) (VP4)
I/O
High
113
MCD6 (VG2) (VP5)
I/O
High
114
MCD7 (VG3) (VP6)
I/O
High
115
MCD8 (VG4) (VP7)
I/O
High
116
MCD9 (VG5) (VP8)
I/O
High
117
MCD10 (VG6) (VP9)
I/O
High
118
MCD11 (VG7) (VP10)
I/O
High
119
MCD12 (VR2) (GRDY)
I/O
High
120
MCD13 (VR3) (VP11)
I/O
High
121
MCD14 (VR4) (VP12)
I/O
High
122
MCD15 (VR5) (VP13)
I/O
High
Note: Pin names in parenthesis (...) indicate alternate functions.
If ICTENA# is low with RESET# low, a rising edge on XTALI will put the chip into "In circuit Test" (ICT) mode. In ICT mode, all digital signal
pins become inputs which are apart of a long path starting at ENA VDD (pin 62) and proceeding to lower pin numbers around the c hip to pin
1 then to pin 208 and ending at VSYNC (pin 64). If all pins in the path are high, the VSYNC output will be high. If any pin is low, the VSYNC
output will be low. Thus the chip can be checked in circuit to determine if all pins are connected properly by toggling all pins one at a time
and observing the effect on VSYNC. XTALI must be toggled last because rising edges on XLTAI with ICTENA# high or RESET# high will exit
ICT mode. As a side effect, ICT mode effectively 3-states all pins except VSYNC. If TSENA# is low with RESET# low, a rising edge on
XTLAI will 3-state all pins. An XTALI rising edge without enabling conditions exits 3-state.
For the ZV Port interface, Y0-7 correspond to VP0-7, and UV0-7 correspond to VP8-15
5 – 36
Summary of Contents for UP-5700
Page 139: ...1 UP 5700 Main PWB CHAPTER 10 PWB LAYOUT A side 10 1 ...
Page 140: ...2 UP 5700 CPU PWB A side UP 5700 CPU PWB B side 10 2 ...
Page 141: ...3 UP 5700 KEY I F PWB A side CN2 UP 5700 KEY I F PWB B side 10 3 ...
Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...
Page 145: ...7 2 Sub PWB Side A Side B 10 7 ...