Protocol Analysis
R&S
®
RTM20xx
166
User Manual 1317.4726.02 ─ 01
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Stop condition: a rising slope on SDA while SCL is high
Fig. 11-4: I2C write access with 7-bit address
Address types: 7-bit and 10-bit
Slave addresses can be 7 or 10 bits long. A 7-bit address requires one byte, 7 bits for
the address followed by the R/W bit.
A 10-bit address for write access requires two bytes: the first byte starts with the reserved
sequence 11110, followed by the two MSB of the address and the write bit. The second
byte contains the remaining 8 LSB of the address. The slave acknowledges each address
byte.
Fig. 11-5: 10-bit address, write access
A 10-bit address for read access requires three bytes. The first two bytes are identical to
the write access address. The third byte repeats the address bits of the first byte and sets
the read bit.
Fig. 11-6: 10-bit address, read access
Trigger
The R&S
RTM can trigger on various parts of I²C messages. The data and clock lines
must be connected to the input channels, triggering on math and reference waveforms
is not possible.
You can trigger on:
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Start or stop condition
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Repeated start condition
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Transfer direction (read or write)
I²C (Option R&S RTM-K1)
