RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide
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5-3
5.2.2 Transmitter HDLC Operation
The format of the data input to the MDP is in groups of 8-bit bytes. As in the normal synchronous parallel data mode, the
least significant bit of the byte is transmitted first.
Flag Transmission and Reception
In HDLC mode, the MDP will send continuous flags with no zero sharing (i.e., 0111111001111..) until the host loads data
into the Transmit Data Buffer, TBUFFER (10h). Thus, the MDP defaults to transmitting time-fill and keeps the receiving link
station active. The status bit FLAGS (0Ah:1) is set to indicate that the MDP is transmitting the flag sequence.
Information Field Transmission and Reception
If the FIFO is not enabled (FIFOEN bit = 0), if the next byte is not loaded into TBUFFER within the next eight bit times, the
MDP interprets this as the end of a frame. If the FIFO is enabled (FIFOEN bit = 1), the TEOF bit must be set by the host to
indicate that the next byte to be written into TBUFFER is the last byte in the frame. The host must reset the TEOF bit after
writing the last byte of the current frame and before writing the first byte of the next frame.
FCS and Ending Flag Transmission and Reception
Following the detection end of frame, the MDP automatically sends the FCS and ending flag. Status bit CRCS (0Ah:2)is set
just before the highest order bit is sent to indicate that the FCS is being transmitted. Once the host sees this bit set, the first
byte of the next frame can be loaded. In this case, the ending flag serves as the beginning flag for the next frame. The MDP
resets the CRCS bit when the ending flag is transmitted. At the same time, the MDP sets the FLAGS bit.
After the FCS transmission (immediately following bit x0), the MDP sends one flag to signify the end of the current frame and
the beginning of the next frame. After the final zero in a flag is transmitted, the MDP looks to see if the host has loaded new
data into TBUFFER. If no new data is loaded before this time, another flag is sent. Therefore, if more than one flag between
frames is desired, the host must wait N-1 multiples of eight bit times after FLAGS is set by the MDP to load new data into
TBUFFER, where N is the number of flags. The host then has seven bit times in which to load new data and thus prevent
another flag from being sent. For example, if three flags are desired between frames, the host must wait at least 16 bit times
and not more than 23 bit times after FLAGS is set by the MDP.
Abort/Idle Sequence Transmission and Reception
An abort/idle sequence can be sent by the host setting the MHLD bit (07h:0). The MDP stops sending any normal frame
transmission, as well as continuous flag transmission, and sends continuous ones. To stop sending continuous ones, the
host must reset MHLD. Then, if no new data is loaded into TBUFFER, the MDP sends continuous flags. If new data is
loaded into TBUFFER, the MDP sends a beginning flag and then the data in TBUFFER.
5.2.3 Receiver HDLC Operation
The format of the data output to the host is in groups of 8-bit bytes. As in the normal synchronous parallel data mode, the
least significant bit of the byte is transmitted first.
Flag Transmission and Reception
The MDP receiver continually searches for the flag data pattern. When one or more flags are detected, status bit SYNCD
(0Ah:0) is set. The flags themselves are not presented to the host through the receiver data buffer RBUFFER (00h). The
host must service the RDBF interrupt while waiting for the SYNC bit to be set to a 1 in order to clear the Receive FIFO of any
unwanted or left- over characters and to ensure the alignment of the SYNCD bit with the received flag.
The MDP can also detect consecutive flags with zero-sharing.
Information Field Transmission and Reception
Received data between flags is passed to the host through the RBUFFER by the use of the handshaking bit RDBF (1Eh:0).
The host must wait for RDBF to be set by the MDP before reading the status bits, followed by the received data in
RBUFFER. Note that the RBUFFER and Receive FIFO can accumulate 144 bytes before overflowing. If the host does not
read the data within 16 byte times, the data in RBUFFER will be overwritten by the next received byte and the Overrun Error
bit (0Ah:3) will be set. The flag sequence and abort/idle sequence are not presented to the user. The receiver determines
where the FCS field is by detecting the ending flag. There is at least a 16-bit time delay in the reception of data.
FCS and Ending Flag Transmission and Reception
Upon the receipt of an ending flag in the current frame (which may also be the beginning flag of the next frame), the receiver
checks the data in the FCS register. If the FCS register remainder is correct, the PE bit (0Ah:5) is left a zero. If the
remainder is incorrect, the PE bit is set. The FCS field is also passed to the host, in case the host wishes to do his own CRC
checking. The receiver will set the SYNCD bit and the PE bit (if the MDP detected a frame with a bad CRC) after sending the
FCS to the host. The MDP presets the FCS register to all ones after one or more flags are received.
Summary of Contents for RC336DPFL
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