RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide
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Table 3-1. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Location
Default
Name/Description
TM
0Fh:2
–
Test Mode. When set, status bit TM indicates that the MDP is in RDL test mode. The
TM bit will be set when RLSD turns off at the start of RDL, and will reset less than 100
ms prior to RLSD turning back on at the end of RDL. (V.22 bis, V.22, Bell 212A)
TONEA
0Bh:7
–
Tone A Detected. When set, status bit TONEA indicates that energy is present on the
line within the tone detector A passband and above its threshold. The bandpass filter
coefficients are host programmable in DSP RAM.
TONEB
0Bh:6
–
Tone B Detected. When set, status bit TONEB indicates that energy is present on the
line within the tone detector B passband and above its threshold. The bandpass filter
coefficients are host programmable in DSP RAM.
TONEC
0Bh:5
–
Tone C Detected. When set, status bit TONEC indicates that energy is present on the
line within the tone detector C passband and above its threshold. The bandpass filter
coefficients are host programmable in DSP RAM. The TONEC filter is preceded by a
squarer in order to facilitate detection of difference tones. This squarer may be
disabled with the SQDIS bit (see SQDIS bit).
TPDM
08h:6
0
Transmitter Parallel Data Mode. When control bit TPDM is set, the MDP accepts
data for transmission from the TBUFFER (10h) rather than the TXD input. (See TDBE
and RTS.) Note: The TPDM bit must be set to a 1 in HDLC mode (HDLC bit = 1).
TXCLK
13h:1-0
0
Transmit Clock Select. The TXCLK control bits designate the origin of the transmitter
data clock. NEWC must be set to initiate TXCLK change. The TXCLK encoding is:
TXCLK
Transmit Clock
0
Internal
2
External (XTCLK)
3
Slave (~RDCLK)
When the external clock is selected, an external clock must be supplied to the XTCLK
input pin. The external clock signal must have a duty cycle of 50% and must be within
±0.01% of the nominal TDCLK frequency (the actual frequency of TDCLK as measured
when internal clock is selected). TDCLK will be phase locked to XTCLK when the
external clock option is selected.
When the slave clock is selected, the transmitter clock (TDCLK) is phase locked to the
receiver clock (~RDCLK).
TXFNF
0Dh:1
-
Transmitter FIFO Not Full. When set, status bit TXFNF indicates that the transmitter
FIFO is not full and the host may continue to write data to the TBUFFER. When reset,
TXFNF indicates that the transmitter FIFO is full. (TPDM = 1, FIFOEN = 1)
TXHF
01h:2
0
Transmitter FIFO Half Full. When set, status bit TXHF indicates that there are 8 or
more bytes in the 16-byte Transmitter FIFO buffer. When reset, TXHF indicates that
there are less than 8 bytes in the Transmitter FIFO buffer. (TPDM = 1, FIFOEN = 1)
An interrupt mask is available to allow an interrupt request to be generated when TXHF
transitions from reset to set or from set to reset (the interrupt will occur as the FIFO
fills above the half-full point and as it empties below the half-full point) (see Section 4,
Function 17).
TXP
11h:0
0
Transmit Parity Bit (or 9th Data Bit). Control bit TXP contains the stuffed parity bit
(or ninth data bit) for transmission when parity is enabled (PEN = 1), stuff parity is
selected (PARSL = 00), and word size is set for 8 bits per character (WDSZ = 11). The
host must load the stuffed parity bit (or 9th data bit) into TXP before loading the other 8
bits of data in TBUFFER.
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