RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide
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9-5
9.4 HANDSHAKE MONITORING
9.4.1 V.8 Octet Monitoring
During the V.8 (Phase 1) procedure the received V.8 octets can be read from the interface memory RBUFFER register by
clearing bit 305h:3 in the V.8 host control bits. The procedure is the same as accessing receive data during normal data
mode.
Handshake Phase Monitoring
During the V.8/V.34 handshake, the secondary channel data buffers display the “state” of the receiver (SECRXB) and the
transmitter (SECTXB). Bits 5, 6 and 7 of these buffers indicate the phase of the handshake (Table 9-9 and Table 9-10).
Using the New Status (NEWS) function, an interrupt can be generated whenever a change occurs to SECRXB and SECTXB.
The NEWS masks for these locations are 370h and 371h, respectively. For a full description, refer to Section 4.
Table 9-9. Receiver Handshake Phase and States
Register
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16
(SECRXB)
Receiver Handshake Phase
Receiver Handshake Phase State
Bits 7-5: Receiver Handshake Phase.
Bit 7
Bit 6
Bit 5
Dec
Value
Handshake Phase (ITU Specification)
0
0
0
0
Phase 1 (V.8)
0
0
1
1
Phase 2 (V.34)
0
1
0
2
Phase 3 (V.34)
0
1
1
3
Phase 4 (V.34)
1
0
0
4
Phase 4 Rate Renegotiation (V.34)
Bits 4-0: Receiver Handshake Phase States.
Phase 1
Receiver Handshake Phase 1 States
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State
Number
Originate Mode Receiver State
Answer Mode Receiver State
0
0
0
0
0
00
Looking for ANSam
Looking for CI or CM
0
0
0
0
1
01
Found ANSam, looking for JM
Found CI, looking for CM
0
0
0
1
0
02
Found JM
Found CM, looking for CJ
0
0
0
1
1
03
CJ detected
Phase 2
See Figure 9-2.
Phase 3
See Figure.
Phase 4
See Figure 9-4.
Summary of Contents for RC336DPFL
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