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RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide

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Table 2-2. MDP Signal Definitions (Cont'd)

Label

I/O Type

Signal Name/Description

PARALLEL HOST INTERFACE

Address, data, control, and interrupt hardware interface signals allow MDP connection to an 8086-compatible microprocessor bus. With the

addition of external logic, the interface can be made compatible with a wide variety of other microprocessors such as the 6502, 8086 or 68000.

The microprocessor interface allows a microprocessor to change MDP configuration, read or write channel and diagnostic data, and supervise

MDP operation by writing control bits and reading status bits.

D0–D7

IA/OB

Data Lines. Eight bidirectional data lines (D0–D7) provide parallel transfer of data between the host and the MDP.
The most significant bit is D7. Data direction is controlled by the Read Enable and Write Enable signals.

RS0–RS4

IA

Register Select Lines. The five active high register select lines (RS0–RS4) address interface memory registers
within the MDP interface memory. These lines are typically connected to the five least significant lines (A0–A4) of

the address bus.

The MDP decodes RS0 through RS4 to address one of 32 internal interface memory registers (00–1F). The most

significant address bit is RS4, while the least significant address bit is RS0. The selected register can be read from

or written into via the 8-bit parallel data bus (D0–D7). The most significant data bit is D7, while the least significant

data bit is D0.

~CS

IA

Chip Select. ~CS selects the MDP for microprocessor bus operation. ~CS is typically generated by decoding host
address bus lines.

~READ

IA

Read Enable. During a read cycle (~READ asserted), data from the selected interface memory register is gated
onto the data bus by means of three-state drivers in the MDP. These drivers force the data lines high for a one bit,

or low for a zero bit. When not being read, the three-state drivers assume their high-impedance (off) state.

~WRITE

IA

Write Enable. During a write cycle (~WRITE asserted), data from the data bus is copied into the selected MDP
interface memory register, with high and low bus levels representing one and zero bit states, respectively.

IRQ

OA

Interrupt Request. The MDP IRQ output may be connected to the host processor interrupt request input in order

to interrupt host program execution for immediate MDP service. The IRQ output can be enabled in the MDP

interface memory to indicate immediate change of conditions. The use of IRQ is optional depending upon MDP

application. The IRQ output is driven by a TTL-compatible CMOS driver.

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Summary of Contents for RC336DPFL

Page 1: ...RCVDL56DPFL SP RCV56DPFL SP and RCV336DPFL SP Modem Data Pump Designer s Guide Preliminary Order No 1119 February 27 1997 ...

Page 2: ... any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent rights of Rockwell International other than for circuitry embodied in Rockwell products Rockwell International reserves the right to change circuitry at any time without notice This document is subject to change without notice K56flex is a t...

Page 3: ...AND WRITE EXAMPLES 4 5 4 4 CHANGES TO RAM ADDRESSES 4 5 4 5 DSP RAM DATA SCALING 4 10 5 HDLC OPERATION 5 1 5 1 HDLC FRAMES 5 1 5 2 OPERATION 5 2 5 2 1 Transmitter and Receiver Setup 5 2 5 2 2 Transmitter HDLC Operation 5 3 5 2 3 Receiver HDLC Operation 5 3 5 3 EXAMPLE APPLICATION 5 4 5 3 1 Transmitter Example Tx FIFO Disabled 5 4 5 3 2 Transmitter Example Tx FIFO Enabled 5 4 5 3 3 Receiver Example...

Page 4: ...N MODE 8 2 8 2 1 General 8 2 8 2 2 ECM Frame Structure 8 22 8 3 SIGNAL RECOGNITION ALGORITHM 8 22 9 V 8 OPERATION CONSIDERATIONS 9 1 9 1 V 8 ORIGINATING MODEM OPERATING PROCEDURE 9 1 9 1 1 Originating Without CI Option Default 9 1 9 1 2 Originating With CI Option 9 1 9 2 V 8 ANSWERING MODEM OPERATING PROCEDURE 9 1 9 3 V 8 AND AUTOMODE 9 4 9 4 HANDSHAKE MONITORING 9 5 9 4 1 V 8 Octet Monitoring 9 5...

Page 5: ...erface 12 7 13 SPEAKERPHONE CONFIGURATION 13 1 13 1 INTERFACE MEMORY REGISTERS 13 1 13 1 1 DTMF and Dual Tone Modes 13 1 13 2 VOICE PATHS 13 2 13 2 2 Volume and Microphone Level Control 13 8 13 2 3 Voice Loopback Sidetone Feature 13 8 13 2 4 Voice Record Playback and Tone Detector Control Register Address 43E 13 8 13 2 5 Room Monitor Mode 13 9 13 2 6 Voice Idle Mode 13 9 13 2 7 Business Audio Samp...

Page 6: ...egotiation Process 4 27 Figure 5 1 HDLC Frame 5 2 Figure 5 2 HDLC Signal Timing 5 6 Figure 6 1 Auto Dial Sequence and Dial Digits 6 3 Figure 6 2 Host Flowchart Originating Automode 6 4 Figure 6 3 Host Flowchart Answering Automode 6 5 Figure 6 4 Modem Self Test Results Read Procedure 6 7 Figure 7 1 Interface Schematic 144 Pin TQFP 7 7 Figure 7 2 Typical Line Interface 7 8 Figure 7 3 Typical Interfa...

Page 7: ...tructure 8 23 Figure 8 21 Phase C Format 8 24 Figure 8 22 ECM Frame Structure 8 25 Figure 8 23 ECM Message Protocol Example 8 26 Figure 8 24 PPS and PPR Frame Structure 8 27 Figure 8 25 FSK Signal Recognition Algorithm 8 28 Figure 9 1 Phase 2 Receiver States 9 7 Figure 9 2 Phase 2 Transmitter States 9 7 Figure 9 3 Phase 3 States 9 8 Figure 9 4 Phase 4 States 9 8 Figure 11 1 ADPCM Rx Coder 11 2 Fig...

Page 8: ...3 Table 4 4 TONEA TONEB and TONEC DSP RAM Addresses Hex 4 19 Table 4 5 TONEA TONEB and TONEC Default Values Hex 4 19 Table 4 6 Example Tone Detector Filter Coefficients 4 21 Table 4 7 V 34 Rate Sequence Mask Bit Assignments 4 33 Table 4 8 V 34 Remote Mode Data Rate Capability Bit Assignments 4 34 Table 6 1 Interrupt Request Bits 6 2 Table 6 2 Auto Dial Default Values 6 2 Table 7 1 Modem Pin Noise ...

Page 9: ...CV336DPFL SP Designer s Guide 1119 ix Table 14 1 K56flex Data Rate Versus Configuration and Data Rate Mask Values 14 2 Table 14 2 K56flex Data Rate Versus Speed Bit Values 14 2 Table 14 3 ARA Values 14 6 Table 14 4 Speed Selection 14 6 ...

Page 10: ...RCVDL56DPFL SP RCV56DPFL SP and RCV336DPFL SP Designer s Guide x 1119 This page is intentionally blank ...

Page 11: ...ates As a V 34 data modem the MDP can operate in 2 wire full duplex synchronous asynchronous modes at rates up to 33600 configuration for line conditions the MDP can connect at the highest data rate that the channel can support from 33600 bps to 2400 bps with automatic fallback to V 32 bis Internal HDLC support eliminates the need for an external serial input output SIO device in the DTE for produ...

Page 12: ...data plus audio in ITU T V 61 mode Voice silence detection and handset echo cancellation Handset headset or half duplex speakerphone Full duplex speakerphone optional Acoustic and line echo cancellation Programmable microphone AGC Microphone volume selection and muting Speaker volume control and muting room monitor ADPCM voice mode optional Voice pass through mode TTL and CMOS compatible DTE inter...

Page 13: ...guration Transmitted Data Spectrum The transmitter spectrum is shaped by raised cosine filter functions as follows Configuration Raised Cosine Filter Function V 34 V 32 bis V 32 V 17 V 33 V 29 Square root of 12 5 V 27 ter Bell 208 Square root of 50 V 22 bis V 22 Bell 212A Square root of 75 RTS CTS Response Time The response times of CTS relative to a corresponding transition of RTS are listed Tabl...

Page 14: ...TCM 1800 9600 2400 4 1 32 V 32 bis 7200 TCM TCM 1800 7200 2400 3 1 16 V 32 bis 4800 QAM 1800 4800 2400 2 0 4 V 32 9600 TCM TCM 1800 9600 2400 4 1 32 V 32 9600 QAM 1800 9600 2400 4 0 16 V 32 4800 QAM 1800 4800 2400 2 0 4 V 22 bis 2400 QAM 1200 2400 2400 600 4 0 16 V 22 bis 1200 DPSK 1200 2400 1200 600 2 0 4 V 22 1200 DPSK 1200 2400 1200 600 2 0 4 V 22 600 DPSK 1200 2400 600 600 1 0 4 V 23 1200 75 F...

Page 15: ...and RING input 15 dBm at RIN Note A 6 dB pad is required between TIP and RING and the RIN input Receiver Timing The timing recovery circuit can track a frequency error in the associated transmit timing source of 0 035 V 22 bis or 0 01 other configurations Carrier Recovery The carrier recovery circuit can track a 7 Hz frequency offset in the received carrier Clamping Received Data RXD is clamped to...

Page 16: ...can be sent to the MDP ADPCM codec for decompression then to the digital to analog converter DAC by the host Receive Voice 16 bit received voice samples from the MDP analog to digital converter ADC can be sent to the ADPCM codec for compression and then be read by the host Voice Pass Through Mode Transmit Voice 16 bit transmit voice samples can be sent to the MDP DAC from the host Receive Voice 16...

Page 17: ...patterns The RTSDT status bit indicates the state of the remote RTS signal This feature may be used to clamp unclamp the local RLSD and RXD signals in response to a change in the remote RTS signal in order to simulate controlled carrier operation in a constant carrier environment The MDP automatically clamps and unclamps RLSD Auto Dialing and Auto Answering Control The host can perform auto dialin...

Page 18: ... 74 DMA Support Interrupt Request Lines DMA support is available in synchronous asynchronous and HDLC parallel data modes Control bit DMAE enables and disables DMA support When DMA support is enabled the MDP RI and DSR lines are assigned to Transmitter Request TXRQ and Receiver Request RXRQ hardware output interrupt request lines respectively The TXRQ and RXRQ signals follow the assertion of the T...

Page 19: ...intended to activate logic on its falling edge high to low transition is called active high e g TDCLK When a clock input is associated with a small circle the input activates on a falling edge If no circle is shown the input activates on a rising edge The pin assignments for the MDP packaged in a single 144 pin TQFP are shown in Figure 2 4 and are listed in Table 2 1 The hardware interface signals...

Page 20: ...IN V 24 SERIAL DTE INTERFACE RDCLK TDCLK XTCLK TXD RXD RTS CTS DTR DSR RLSD RI Figure 2 1 RCV336DPFL SP Modem Functional Interface Signals XMD180F1 FID RC56DPFL RCV56DPFL RCV56DPFL SP MODEM DATA PUMP R6765 144 PIN TQFP RS0 RS4 CRYSTAL XTLI XTLO TELEPHONE LINE TELEPHONE AUDIO INTERFACE INTERFACE TELEPHONE LINE RLYA RLYB RINGD RIN TXA1 TXA2 TELIN TELOUT MICV MICM SPK SPKMD RXA TXA 5V AGND DGND POWER...

Page 21: ...ELIN TELOUT MICV MICM SPK SPKMD RXA TXA 5V AGND DGND POWER SUPPLY HOST PROCESSOR DECODER CS READ WRITE DATA BUS 8 D0 D7 ADDRESS BUS 5 A0 A4 RESET IRQ MIC SPEAKER SPKR MIC TELEPHONE LINE TELOUT TELIN V 24 SERIAL DTE INTERFACE RDCLK TDCLK XTCLK TXD RXD RTS CTS DTR DSR RLSD RI RCDL56DPFL RCVDL56DPFL RCVDL56DPFL SP MODEM DATA PUMP R6775 144 PIN TQFP Figure 2 3 RCVDL56DPFL SP Modem Functional Interface...

Page 22: ...AVAA SPK TXA1 TXA2 VREF VC MICV RIN AGNDM RES2 MICM MICBIAS RLYB SPKMD AVDD RESERVED RESERVED SET3V NC MCNTRLSIN MCLKIN MTXSIN MSCLK MRXOUT MSTROBE RLYA AGND AVDD VSUB GND VSTROBE VRXOUT VSCLK VTXSIN VCLKIN VCNTRLSIN IASLEEP GND PLLGND RESERVED RESERVED RS2 RS3 RS4 CS WRITE READ NC RDCLK WKRES 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 ...

Page 23: ...XA2 O DD Line Audio Interface 98 RESERVED NC 27 VREF REF VC through capacitors 99 RESERVED NC 28 VC REF AGND through capacitors 100 RESERVED NC 29 MICV I DA Line Audio Interface 101 RESERVED NC 30 RIN I DA Line Audio Interface 102 RESERVED NC 31 AGNDM GND AGND 103 SA2CLK DI To VSTROBE 53 32 RES2 PIF RESET SIF Reset circuit 104 SR2IO DI To VCNTRLSIN 58 33 MICM I DA Line Audio Interface 105 NC NC 34...

Page 24: ...H2 IA VDD through 10K Ω 69 READ IA Host Parallel Interface 141 XTLI I Crystal Clock Circuit 70 NC NC 142 NC NC 71 RDCLK OA DTE Serial Interface 143 XTLO O Crystal Clock Circuit 72 WKRES OA Peripheral device 144 D0 IA OB Host Parallel Interface Notes 1 I O types MI Modem interconnect IA IB Digital input OA OB Digital output I DA Analog input O DD O DF Analog output DI Device interconnect 2 NC No ex...

Page 25: ...ode Reserved Function May be connected to internal circuit Leave open XCLK OA System Clock Output clock at the external crystal frequency which runs during MDP Normal Mode and is turned off during Sleep Mode YCLK OA System Clock Divided by 2 Output clock at one half the external crystal frequency which runs during MDP Normal Mode and is turned off during Sleep Mode SYCLK OA System Clock Divided by...

Page 26: ... internal interface memory registers 00 1F The most significant address bit is RS4 while the least significant address bit is RS0 The selected register can be read from or written into via the 8 bit parallel data bus D0 D7 The most significant data bit is D7 while the least significant data bit is D0 CS IA Chip Select CS selects the MDP for microprocessor bus operation CS is typically generated by...

Page 27: ...IA Data Terminal Ready In K56flex V 34 V 32 bis V 32 V 22 bis V 22 or Bell 212A configuration activating DTR initiates the handshake sequence provided that the DATA bit is a 1 If in answer mode the MDP immediately sends answer tone In V 21 V 23 or Bell 103 configuration activating DTR causes the MDP to enter the data state provided that the DATA bit is a 1 If in answer mode the MDP immediately sen...

Page 28: ...Relay B Control The RLYB open collector output can directly drive a 5V reed relay coil with a minimum resistance of 360 ohms 13 9 mA max 5 0V and a must operate voltage no greater than 4 0 VDC A clamp diode such as a 1N4148 should be installed across the relay coil An external transistor can be used to drive heavier loads e g electro mechanical relays RLYB is controlled by host setting resetting o...

Page 29: ...10k Ω RESERVED Reserved Function May be connected to internal circuit Leave open MODEM INTERCONNECT GPO0 DI To RDCLK SLEEPO DI To IASLEEP IASLEEP DI To SLEEPO MSCLK DI To IA1CLK CLKOUT DI To MCLKIN VCLKIN SR1IO DI To MCNTRLSIN SR3IN DI To VRXOUT IA1CLK DI To MSCLK SA1CLK DI To MSTROBE SR4OUT DI To MTXSIN MCLKIN DI To CLKOUT VCLKIN DI To CLKOUT MSTROBE DI To SA1CLK VSTROBE DI To SA2CLK MCNTRLSIN DI...

Page 30: ...C Type OA 0 4 I LOAD 1 6 mA Type OB 0 4 I LOAD 0 8 mA Type OD 0 75 I LOAD 15 mA Three State Off Current I TSI 10 µADC V IN 0 4 to V CC 1 Table 2 4 Analog Electrical Characteristics Signal Name Type Characteristic Value RIN TELIN I DA Input Impedance 70K Ω MICM MICV AC Input Voltage Range 1 1 VP P Reference Voltage 2 5 VDC TXA1 TXA2 O DD Minimum Load 300 Ω Maximum Capacitive Load 0 µF Output Impeda...

Page 31: ...5VD 0 5 V Operating Temperature Range T A 0 to 70 C Storage Temperature Range T STG 55 to 125 C Analog Inputs V IN 0 3 to 5VA 0 3 V Voltage Applied to Outputs in High Impedance Off State V HZ 0 5 to 5VD 0 5 V DC Input Clamp Current I IK 20 mA DC Output Clamp Current I OK 20 mA Static Discharge Voltage 25 C V ESD 2500 V Latch up Current 25 C I TRIG 200 mA Table 2 7 Host Bus Interface Timing Paramet...

Page 32: ...a Host Bus Read b Host Bus Write A minimum delay of 3 times the YCLK cycle time is required from the rising edge of WRITE to the falling edge of the next selected READ or WRITE YCLK crystal frequency 2 A minimum delay of 20 ns is required from the rising edge of READ to the falling edge of the next selected READ or WRITE 1026F2 7 PIF WF Figure 2 5 Host Bus Interface Waveforms ...

Page 33: ...OR SYNCHRONOUS MODE ONLY THERE IS NO RELATIONSHIP BETWEEN NOTE TXD AND TDCLK IN ASYNCHRONOUS MODE RDCLK 4800 BPS RXD 4800 BPS RDCLK 9600 BPS RXD 9600 BPS NOTE THIS FIGURE IS VALID FOR SYNCHRONOUS MODE ONLY THERE IS NO RELATIONSHIP BETWEEN NOTE RXD AND RDCLK IN ASYNCHRONOUS MODE a Transmit b Receive 1026F2 8 SIF WF Figure 2 6 DTE Serial Interface Waveforms ...

Page 34: ...t the total harmonic distortion seen at the RXA input to the MDP be at least 45 dB RC336DPFL or 65 dB RC56DPFL below the minimum level of received signal Due to the wider bandwidth requirements in K56flex and V 34 the DAA must maintain linearity from 10 Hz to 3954 Hz RC336DPFL or 4000 Hz RC56DPFL Note that the major source of non linear distortion in a DAA is the line transformer A suitable line t...

Page 35: ...parameter values from DSP RAM through interface memory 3 1 1 Interface Memory Map An interface memory map of the 32 addressable registers in the MDP is shown in Figure 3 1 These 8 bit registers may be read or written during any host read or write cycle In order to operate on a single bit or a group of bits in a register the host processor must read a register then mask out unwanted data When writi...

Page 36: ...ion CONF 11 BRKS PARSL TXV RXV V23HDX TEOF TXP 10 Transmit Data Buffer TBUFFER Voice Transmit Buffer VBUFT 0F RLSD FED CTS DSR RI TM RTSDT V54DT 0E RTDET BRKD RREDT SPEED 0D P2DET PNDET S1DET SCR1 U1DET TXFNF 0C AADET ACDET CADET CCDET SDET SNDET RXFNE RSEQ 0B TONEA TONEB TONEC ATV25 ATBEL DISDET EQMAT 0A PNSUC FLAGDT PE FE OE CRCS FLAGS SYNCD 09 NV25 CC DTMF ORG LL DATA RRTSE DTR 08 ASYN TPDM V21...

Page 37: ...N is set asynchronous mode is selected when 0 synchronous mode is selected When the ASYN bit changes from a 0 to a 1 the asynchronous to synchronous converter is configured according to the EXOS PEN STB and WDSZ bits at that time EXOS PEN STB and WDSZ must be configured before ASYN changes from a 0 to a 1 ASYN may be used to switch between synchronous and asynchronous modes only when RTS is OFF an...

Page 38: ...eset the MDP will transmit parallel data from the TBUFFER This bit is valid only when TPDM 1 CADET 0Ch 5 CA Detector When set status bit CADET indicates that a CA sequence has been detected This bit is reset by the MDP when a AC sequence is detected This bit is not valid during rate renegotiation V 32 bis V 32 CC 09h 6 0 Controlled Carrier When control bit CC is set and the LL bit is set the MDP o...

Page 39: ...M 4800 C2 V 34 TCM 2400 C1 V 34 Cleardown C0 See Note 1 V 33 TCM 14400 31 V 33 TCM 12000 32 V 33 TCM 9600 34 V 33 TCM 7200 38 V 32 bis TCM 14400 76 V 32 bis TCM 12000 72 V 32 TCM 9600 74 V 32 9600 75 V 32 bis TCM 7200 78 V 32 4800 71 V 32 bis V 32 Cleardown 70 See Note 1 V 17 TCM 14400 B1 V 17 TCM 12000 B2 V 17 TCM 9600 B4 V 17 TCM 7200 B8 V 29 9600 14 V 29 7200 12 V 29 4800 11 V 27 ter 4800 02 V ...

Page 40: ...uence has been completed and any data present at TXD serial mode or in TBUFFER parallel mode will be transmitted see TPDM CTS response times from an RTS ON or OFF transition after the MDP has completed a handshake are shown in Table 1 3 The CTS OFF to ON response time is programmable in DSP RAM DATA 09h 2 1 Data Control bit DATA is used to prevent the transmitter from entering and proceeding with ...

Page 41: ...isfies all DTMF criteria except on time off time and cycle time The encoded DTMFW Output Word 1Bh 3 0 value is available when DTDET is set DTMF 09h 5 1 DTMF Select When the MDP is configured for dialing mode CONF 81h the MDP will dial using DTMF tones or pulses When control bit DTMF is set the MDP will dial using DTMF tones When DTMF is reset the MDP will dial using pulses The DTMF bit can be chan...

Page 42: ... Enable When control bit EPT is set an unmodulated carrier is transmitted for 185 ms SEPT 0 or 30 ms SEPT 1 followed by 20 ms of no transmitted energy prior to the transmission of the training sequence When EPT is reset neither the echo protector tone nor the 20 ms of no energy are transmitted prior to the transmission of the training sequence V 33 V 17 V 29 V 27 The echo protector tone is typical...

Page 43: ... for RDBF bit RXRQ signal is host programmable in DSP RAM See Section 4 for a detailed description about FIFO operation TPDM 1 FLAGDT 0Ah 6 V 21 Channel 2 Flag Detected When set status bit FLAGDT indicates that V 21 Channel 2 Flags 7Eh are being detected V 33 V 17 V 29 V 27 ter FLAGS 0Ah 1 0 Flag Sequence When set status bit FLAGS indicates that the transmitter is sending the Flag sequence in SDLC...

Page 44: ...2 For V 34 set the LL bit V 8 should not be used in V 34 leased line When DTR and DATA bits are set the MDP continuously sends INFO0 until the remote modem is detected V 34 For V 32 bis V 32 do not set LL bit When DTR and DATA bits are set the MDP continuously sends its preamble signal until the remote modem is detected If desired set the NV25 bit to prevent answer tone from being sent in answer m...

Page 45: ...h 0 0 New Configuration Control bit NEWC must be set by the host after the host changes the configuration code in CONF 12h or changes any of the following controls bits CEQ 05h 3 DTMF 09h 5 GTE 03h 1 GTS 03h 0 L3ACT 07h 3 LL 09h 3 ORG 09h 4 RTH 13h 2 3 RXV 11h 3 SFRES 1Ah 7 SLEEP 15h 7 TLVL 13h 7 4 TXCLK 13h 1 0 TXV 11h 4 V21S 08h 5 or V23HDX 11h 2 This informs the MDP to implement the new configu...

Page 46: ...ia P2DET 0Dh 7 0 P2 Sequence Detected When status bit P2DET is set the MDP is detecting the P2 portion of the training sequence When P2DET is reset P2 is not being detected V 33 V 17 V 29 V 27 PARSL 11h 6 5 00 Parity Select Parity Select Control bits PARSL select the method by which parity is generated and checked during the asynchronous parallel data mode ASYN 1 The options are 6 5 Parity Selecte...

Page 47: ...g into loopback When this occurs the MDP clamps RXD to mark resets the CTS DSR and RLSD bits and turns the CTS DSR and RLSD signals to logic 1 The TM bit is set to inform the host of the test status When the RDLE bit is reset no response will be generated V 22 bis RDWK 15h 5 1 Ring Detect Wake up When control bit RDWK is set and the MDP is in sleep mode an incoming ring signal on the RINGD pin wil...

Page 48: ...ent rate negotiations from colliding the MDP will first check for a possible incoming retrain or rate renegotiation before allowing the setting of the RREN bit to be processed This may delay the RREN request by 3 4 ms If a valid retrain or rate renegotiation is detected the request for a RREN will be denied and the RREN bit will be reset to 0 The MDP will then proceed with the received retrain or ...

Page 49: ... Fallback or fall forward retrains may be accomplished in K56flex V 34 V 32 bis V 32 or V 22 bis modes as follows 1 If EARC 0 change CONF to the required configuration code If EARC 1 do not change CONF NOTE Only the data rate within a mode can be changed not the mode e g fallback from V 32 to V 22 bis mode is not possible Do not set the NEWC bit 2 Set the RTRN bit If the remote modem can operate a...

Page 50: ... in response to a change in the remote RTS signal Detection is available in synchronous and asynchronous modes This bit is not valid in FSK modes RXFNE 0Ch 1 Receiver FIFO Not Empty When set status bit RXFNE indicates that the receiver FIFO contains one or more bytes of data When reset bit RXFNE indicates that the receiver FIFO is empty As long as RXFNE 1 or RDBF 1 there is receive data to be read...

Page 51: ...mbled 1s have been detected during handshake This bit is reset at the end of the scrambled 1s sequence V 22 bis V 22 Bell 212 SDET 0Ch 3 S Detector When set status bit SDET indicates that a S sequence has been detected This bit is reset by the MDP at the end of the S sequence V 34 V 32 bis V 32 SECEN 1Ah 0 0 Secondary Channel Enable When control bit SECEN is set the secondary channel is enabled Wh...

Page 52: ...V 34 modes the SPEED status bits indicate the receiver s and transmitter s data rate at the completion of a handshake In K56flex and V 34 asymmetric modes the SPEED status bits indicate the transmitter s data rate and the CONF bits indicate the receiver s data rate at the completion of a handshake SPEED Hex Data Rate bps SPEED Hex Data Rate bps 0 0 300 10 33600 1 600 11 32000 2 1200 12 34000 3 240...

Page 53: ...it STB is reset one stop bit is selected in asynchronous mode when set two stop bits are selected This bit must be configured appropriately before the ASYN bit changes from a 0 to a 1 for asynchronous mode K56flex V 34 V 32 bis V 32 V 22 V 22 bis Bell 212A STOFF 05h 1 0 Soft Turn Off When control bit STOFF is set the transmitter sends a tone at the end of a transmission in V 23 V 21 and Bell 103 c...

Page 54: ... TBUFFER 128 byte extension enabled See TDBIE and TDBIA TDBIA 1Eh 7 Transmit Data Buffer Interrupt Active When the transmit data buffer interrupt is enabled TDBIE is set and register 10 is empty TDBE is set the MDP asserts IRQ and sets status bit TDBIA to indicate that TDBE being set caused the interrupt The host writing to register 10 resets the TDBIA bit and clears the interrupt request due to T...

Page 55: ...origin of the transmitter data clock NEWC must be set to initiate TXCLK change The TXCLK encoding is TXCLK Transmit Clock 0 Internal 2 External XTCLK 3 Slave RDCLK When the external clock is selected an external clock must be supplied to the XTCLK input pin The external clock signal must have a duty cycle of 50 and must be within 0 01 of the nominal TDCLK frequency the actual frequency of TDCLK as...

Page 56: ... voice AGC V21S 08h 5 0 V21 Synchronous In V 21 configuration CONF A0h control bit V21S selects either synchronous V21S 1 or asynchronous V21S 0 mode In V 21 synchronous mode a synchronous transmit clock is provided on the TDCLK pin and a synchronous receive clock is provided on the RDCLK pin During transmit synchronous data may be applied in either serial or parallel form depending on the TPDM bi...

Page 57: ...tern of 8192 bits produced by scrambling a binary 1 with the polynomial 1 x 4 x 7 followed by 64 binary 1s in accordance with ITU T Recommendation V 54 The transmission will be at the modem signaling rate When transmission of the signaling pattern is complete V54T is automatically reset by the DSP V 54 signaling pattern detection is available in both synchronous and asynchronous modes Not valid in...

Page 58: ...les 1 or disables 0 the voice pause When VPAUSE is enabled voice data is not output to the host WDSZ 06h 1 0 0 Data Word Size he WDSZ field sets the number of data bits per character in asynchronous mode as follows V 34 V 32 bis V 32 V 22 V 22 bis Bell 212A B1 B0 Data Bits Character 0 0 5 1 0 6 0 1 7 1 1 8 These bits must be configured appropriately before the ASYN bit changes from a 0 to a 1 for ...

Page 59: ...off during RTDE V 32 82 Lost track of AC AA CA CC during RTDE V 32 84 Timed out waiting for S sequence 1st ORG V 32 85 Timed out waiting for S sequence 2nd ORG V 32 86 Timed out waiting for S sequence 1st ANS V 32 8C FED turned off during TRN sequence 1st ORG V 32 8D FED turned off during TRN sequence 2nd ORG V 32 8E FED turned off during TRN sequence 1st ANS V 32 90 R1 not detected V 32 91 R2 not...

Page 60: ...med out waiting for S Sbar in phase 4 V 34 D5 Timed out waiting for S in phase 4 V 34 D6 Timed out waiting for MP V 34 D7 Timed out waiting for MP V 34 D8 Timed out waiting for E V 34 D9 JP sequence not detected V 34 DA Timed out in transmitter rate renegotiation V 34 DB Reserved DC K56flex timed out looking for energy K56flex DD K56flex timed out in phase 3 K56flex E2 Retrain detected during phas...

Page 61: ... the MEACC bit The DSP tests this bit each sample period RAM can be accessed using one of four methods 1 8 bit read 8 bit write 2 16 bit read 8 bit write 3 16 bit read 16 bit write 4 16 bit read only MDP diagnostics Parameters transferred under the first method have only 8 bits of significance The data is written to and read from MEDAL Data in MEDAM is ignored Parameters transferred using the seco...

Page 62: ...7 13 Dual Tone 1 Frequency 2 281 280 see Note 1 14 Dual Tone 2 Frequency 2 283 282 see Note 1 15 Dual Tone 1 Power Level 2 285 284 see Note 1 16 Dual Tone 2 Power Level 2 287 286 see Note 1 17 New Status NEWS Masking Registers Masking Register for 01 1 247 Masking Register for 0A and 0B 2 246 245 Masking Register for 0C and 0D 2 244 243 Masking Register for 0E and 0F 2 242 241 Masking Register for...

Page 63: ...Level 1 32C Transmit FIFO Extension Enable 1 702 0 Receive FIFO Extension Enable 1 701 0 81 V 34 Spectral Parameters Control 1 105 82 V 34 Phase 2 Power Reduction 1 0E2 85 V 34 Data Rate Mask 2 383 382 K56flex V 34 Transmitter Maximum Data Rate Mask 1 605 K56flex V 34 Receiver Maximum Data Rate Mask 1 604 86 K56flex V 34 Asymmetric Data Rates Enable 1 13F 6 87 V 34 Remote Mode Data Rate Capability...

Page 64: ...f Time DTMF 3 C96 102 Minimum Cycle Time DTMF 3 D96 103 Minimum Dropout Time DTMF 3 F96 104 Maximum Speech Energy DTMF 3 E95 105 Frequency Deviation Low Group DTMF 3 C94 106 Frequency Deviation High Group DTMF 3 E94 107 Negative Twist Control TWIST4 DTMF 3 D95 108 Positive Twist Control TWIST8 DTMF 3 C95 109 Maximum Energy Hit Time DTMF 3 E87 110 ADC Speech Sample Scaling Parameter ADCS ADPCM 3 F2...

Page 65: ...and or MEDAL the MDP resets the MEACC bit and sets the NEWS bit to indicate DSP RAM read completion If the NSIE bit is a 1 IRQ is asserted and NSIA is set to inform the host that setting of the NEWS bit is the source of the interrupt request 5 Upon the completion of IRQ servicing write a 0 into the NEWS bit to clear the NSIA bit and to negate IRQ if no other interrupt requests are pending 4 3 RAM ...

Page 66: ...336DPFL SP Designer s Guide 4 6 1119 START 1 MEMW 1D 5 02h MEADDH 1D 0 3 18h MEADDL 1C 0 7 NEW DATA MEDAL 18 0 7 1 MEACC 1D 7 MEACC 1D 7 0 0 MEMW 1D 5 END N Y 1026F4 1 Method 1 Figure 4 1 Method 1 Example Changing DTMF Tone Duration LSB ...

Page 67: ...ART 1 MEMW 1D 5 02h MEADDH 1D 0 3 02h MEADDL 1C 0 7 NEW LSB DATA MEDAL 18 0 7 1 MEACC 1D 7 MEACC 1D 7 0 02h MEADDH 1D 0 3 03h MEADDL 1C 0 7 NEW MSB DATA MEDAL 18 0 7 1 MEACC 1D 7 MEACC 1D 7 0 0 MEMW 1D 5 END 1026F4 2 Method 2 Y Y Figure 4 2 Method 2 Example Changing RTS CTS Delay ...

Page 68: ...P Designer s Guide 4 8 1119 N START 1 MEMW 1D 5 Ah MEADDH 1D 0 3 B8h MEADDL 1C 0 7 NEW LSB DATA MEDAL 18 0 7 1 MEACC 1D 7 MEACC 1D 7 0 NEW MSB DATA MEDAM 19 0 7 0 MEMW 1D 5 END 1026F4 3 Method 3 Figure 4 3 Method 3 Example Changing TONEA THRESHU ...

Page 69: ... SP and RCV336DPFL SP Designer s Guide 1119 4 9 N START 0 MEMW 1D 5 2h MEADDH 1D 0 3 0Ch MEADDL 1C 0 7 1 MEACC 1D 7 MEACC 1D 7 0 READ MEDAM 19 0 7 READ MEDAL 18 0 7 END 1026F4 4 Method 4 Figure 4 4 Method 4 Example Reading EQM ...

Page 70: ...fter each handshake retrain or rate renegotiation When connected in K56flex the current receiver speed may be read from 2E4h and the transmit speed from 2E5h These locations are updated after each handshake retrain or rate renegotiation The speeds are reported as follows 2E5h or 2E4h Value K56flex V 34 Transmitter Speed 2E5h or V 34 Receiver Speed 2E4h kbps K56flex Receiver Speed 2E4h kbps 0E 33 6...

Page 71: ...on V 32 2 B13 and B14 shall be set to zero when transmitting and ignored during the reception of a rate signal they are reserved for future definition by the ITU T and must not be used by the manufacturers 3 B4 B6 B9 B10 B12 set to zero calls for a GSTN Cleardown V 32 Rate Sequence Bits ITU T defines the V 32 rate sequence bits as follows BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATA 0 0 0 0 1 X ...

Page 72: ...n the RSEQ bit is a 1 The RSEQ bit will turn on when the E sequence is available as well The rate sequence s and E sequence are read from two different RAM locations see Table 4 1 Function 2 The RSEQ bit must be reset by the host after reading the rate sequence s The host may modify the rate sequence in one of two ways Method 1 Description The first and simplest method is to use the rate sequence ...

Page 73: ... 9600 V 32 9600 0711 0711 0311 F311 V 32 9600 V 32 9600 0511 0511 0511 F511 V 32 4800 V 32 4800 V 32 4800 0791 0511 0511 F511 V 32T 9600 V 32 4800 0711 0511 0511 F511 V 32 9600 V 32 4800 0511 0511 0511 F511 V 32 4800 V 32 4800 Table 4 3 R and E Rate Sequences V 32 bis to V 32 bis V32BS 1 Originate Set at R1 Hex R2 Hex R3 Hex E Hex ANS and ORG Answering Configuration Resulting Configuration V 32T 1...

Page 74: ...tten to RAM Notes 1 The compromise equalizer is automatically disabled by the transmitter when sending DTMF tones single tones or dual tones The DTMF levels are not affected by the transmit level bits TLVL The calling tones however are affected by the TLVL bits 2 Maximum output power 0 5 dBm The dialing parameters and their default values are Function Parameter Method Address Hex Default Hex Defau...

Page 75: ...656E 10 143D 3 5A67 11 1209 2 5092 12 1013 1 47CF 13 0E53 0 4000 14 0CC5 1 390A 15 0B61 2 32D6 16 0A24 3 2D4E 17 090A 4 2861 18 080E 5 23FD 19 072E 6 2013 20 0666 7 1C96 21 05B4 For example if TLVL is set for 9 dBm and the required level is 30 dBm the difference is 21 dBm Therefore load addresses 3DBh and 3DAh with 05h and B4h respectively The dynamic range of the scale factor is effective from 6 ...

Page 76: ...s change only when RTS is off 2 The Transmit Level bits TLVL affect output level 3 Power out PO TLVL setting transmitter output gain constant Function 17A New Status NEWS Masking Registers Acc Method See Table 4 1 Addr See Below Function 17B Memory Access Masking Register Acc Method 1 Addr 089h 6 Writing a 1 in the bit location corresponding to the desired bit will cause NEWS to go active when a s...

Page 77: ... Value Hex V 32 bis Average Value Hex 8 1100 1300 9 0F00 1100 10 0D00 0F00 11 0C00 0D00 12 0A00 0C00 13 0900 0A00 15 0700 0800 20 0400 0500 25 0250 0300 30 0150 0180 35 00C0 00D0 40 0070 0080 45 0045 0040 Note Function 23 is not valid until RLSD is ON Function 24 CTS OFF to ON Response Time RTS CTS Delay Acc Method 2 Addr 203h 202h Function 24 determines the CTS off to on response time in 2 wire f...

Page 78: ...ammable coefficients To make the prefilter transparent to use TONEC as a 4th order filter write 7FFFh in coefficients A1 and write 0000 to all other biquad coefficients The implementation of the filters allows user definition of the characteristics of the prefilter and the three tone detectors Table 4 4 provides the DSP RAM address codes for the filter coefficients Table 4 5 shows the default valu...

Page 79: ...FBK Å 7FFFh The default response time is in the order of 0 01 seconds 1026F4 6 Tone Det Level Detect TONEB Bit Tone B Detector AGC Level Detect TONEC Bit Prefilter Squarer Tone C Detector Level Detect TONEA Bit Tone A Detector Biquad 1 Biquad 2 ABS x RXA x Integrator Fixed Gain DAGCRF BBBh DUGAIN 8B9h DSRATE 9BBh x Figure 4 6 Tone Detectors Table 4 4 TONEA TONEB and TONEC DSP RAM Addresses Hex TON...

Page 80: ...gn are greater than one This is because the biquad sections have been implemented as shown in Figure 4 7 The modified values are therefore Function A1 A2 A3 B1 B2 Biquad 1 0 0684 0 1368 0 0684 0 9140 0 4418 Biquad 2 0 0684 0 1368 0 0684 0 7858 0 3960 Next convert the above numbers to fractional 2s complement numbers In this case the default coefficient values for TONEA Function A1 A2 A3 B1 B2 Biqu...

Page 81: ...F19 2225 Hz 0205 FBF9 0206 C147 D22D 0205 0380 0206 C147 D1F8 1270 Hz 02B2 FAA1 02B3 C147 38A4 02B2 00F0 02B3 C147 3871 1650 Hz 0306 F9F9 0307 C147 10A6 0306 010D 0307 C147 106E 980 Hz 0205 FBF9 0206 C147 5337 0205 00B4 0206 C147 530D 1300 Hz 0244 FB7B 0245 C147 35A7 0244 00CA 0245 C147 3574 245 650 Hz 1 08C2 EE7C 08C2 C774 74FE 08C2 1184 08C2 CD4F 6495 360 440 Hz 2 0000 FD36 02CA C63E 7243 02CA 0...

Page 82: ...the counter to increment in order to prolong the freeze time Both addresses 27h1 and 270h may be written to after RLSD 1 Function 31 RLSD Turn On Threshold RLSD_ON Acc Method 2 Addr 135h 134h Function 32 RLSD Turn Off Threshold RLSD_OFF Acc Method 2 Addr 137h 136h RLSD Threshold Offset Acc Method 2 Addr 139h 138h RLSD Overwrite Control Acc Method 1 Addr 10Dh 2 Extended RTH Control Acc Method 1 Add...

Page 83: ...ion 36 AGC Gain Word Acc Method 4 Addr A00h Function 36 is useful for determining the receive level RL at the Receive Analog RXA input The number in RAM is related to the receive level as follows Configuration Equation V 34 V 33 V 17 V 29 V 27 RL N 682 7 52 dB V 32 bis V 32 RL N 682 7 53 dB V 22 bis V 22 Bell 212 V 23 1200 RL N 682 7 48 dB V 21 V 23 75 RL N 682 7 54 dB Bell 103 RL N 682 7 51 dB Wh...

Page 84: ...umber to an eye pattern created by a 4 point signal structure e g V 29 4800 bps in the presence of high level white noise The EQM value is proportional to the square of the radius of the disk around any ideal point The radius increases when signal to noise ratio SNR decreases As the radius approaches the ideal point s boundary values the bit error rate BER increases Curves of BER as a function of ...

Page 85: ...ately 6 degrees with a minimum frequency of 10 Hz in order for the MDP to lock on and track the jitter Equation F N Symbol Rate 216 V 34 F N 27 3 V 32 bis V 32 Where F is the frequency in Hz N is the decimal equivalent of the hex number read from RAM Symbol Rate 2400 2800 3000 3200 or 3429 Function 50 Phase Jitter Amplitude Acc Method 4 Addr 80Dh The phase jitter amplitude estimate is available in...

Page 86: ...tion 61 V 34 Baud Rate Mask BRM Acc Method 1 Addr 101h During the start up handshake the MDP probes the communication channel and determines the available bandwidth This information helps establish the common symbol rate between the modems The following data rate ranges are available for a selected symbol rate Symbol Rate baud Highest Possible V 34 Data Rate bps 2400 21600 2800 26400 3000 28800 32...

Page 87: ...efined each matching the templates defined in ITU T V 34 The Pre emphasis filter selected can be read from the V 34 Pre Emphasis Filter Number address B44h The Pre emphasis negotiation can be ignored by setting bit 100h 1 Pre emphasis Disable PREDIS This bit does not stop the measurement or the transmission of the suggested pre emphasis filter but rather causes the receiver to ignore the suggestio...

Page 88: ... These occupy locations 3B0h to 3BFh The Search table used for determining the best data rate for a given EQM is uniquely organized The search through the table starts at the low address first which represents the lowest data rate and progresses through to the higher data rates as the measured EQM value during training decreases The final measured EQM is compared to the ARA RAM table The EQM value...

Page 89: ...te when Probing SNR is Adverse If the signal to noise ratio SNR is less than the specified threshold the data pump overrides the bandwidth evaluation algorithm and forces the Symbol Rate to 2400 baud This allows the MDP to fallback to 2400 bps if the SNR is poor as defined by this threshold The threshold is located in RAM at address 3C0 and the bit which enables this feature is bit 3A5 5 The defau...

Page 90: ...e Acc Method 1 Address 702h 0 Receive FIFO Extension Enable Acc Method 1 Address 701h 0 Transmitter FIFO TXFIFO The 16 byte TXFIFO is controlled by writing to the FIFOEN bit 04h 4 0 TXFIFO disabled 1 TXFIFO enabled The 128 byte TXFIFO Extension TXFIFOX is controlled by writing to the Transmit FIFO Extension Enable bit 702h 0 0 TXFIFOX disabled 1 TXFIFOX enabled default When the TXFIFO is enabled F...

Page 91: ...e out delay has not elapsed see below Both RDBF and RXFNE will remain set until the RXFIFO is empty Bit 7 Bit 6 Trigger Level No of Bytes 0 0 Trigger level 1 0 1 Trigger level 4 1 0 Trigger level 8 1 1 Trigger level 14 Bit 5 Must be 0 Bits 4 2 Time out Delay Selects the length of idle time that will cause RDBF to be asserted when the RXFIFO is not empty Idle time is the length of time that elapses...

Page 92: ...uses for cases where the local PTT has regulations governing transmission These control bits should be used in their default state and the host need only alter them if required to meet PTT approval Bit 7 Transmitter Enable for the Low Carrier Frequency for 3200 Baud When set the transmitter can use the low carrier frequency for 3200 baud Bit 6 Transmitter Enable for the High Carrier Frequency for ...

Page 93: ... 1 X X X X X X X X X X X 31200 X 1 X X X X X X X X X X X X 33600 1 X X X X X X X X X X X X X The rate mask at 383h 382h controls the data rate for both the transmitter and receiver In other words if the rate mask is limited to 24k bps both the transmitter and receiver rates will be limited to 24k bps If connected in asymmetric mode see Function 86 the transmitter rate may be further limited by the...

Page 94: ...he remote modem s ARA yet the received rate sequence may indicate that the remote modem can support 28800 bps This information may be used for fall forward decisions Bits 14 15 are reserved Table 4 8 V 34 Remote Mode Data Rate Capability Bit Assignments Data Rate V 34 Remote Mode Data Rate Capability MSB Address 209h V 34 Remote Mode Data Rate Capability LSB Address 208h bps B15 B14 B13 B12 B11 B1...

Page 95: ...al is detected and ending when the next signal begins The cycle time parameter is equal to the desired minimum cycle time minus the dropout time The default cycle time parameter is set for 93 0 1 ms with a default drop out time parameter of 5 0 ms To increase or decrease the cycle time parameter value convert the increase decrease into hex and add subtract to from the current value Format 16 bits ...

Page 96: ...s the acceptable negative twist level The twist will vary from one DTMF symbol to another To increase or decrease the parameter value convert the increase decrease into hex and add subtract to from the default value Format 16 bits twos complement positive value Range 0000h to 7FFFh Equation Negative Twist Increase Decrease h Default 18CEh Function 108 Positive Twist Control TWIST8 DTMF Acc Method ...

Page 97: ...umber of octets each octet having the first bit a binary zero with the exception of the last octet that begins with a binary one Control Field The control field defines the function of the frame It may contain a command or response The control field might also contain send or and receive sequence numbers This field can be in one of the following formats 1 Information Transfer Format 2 Supervisory ...

Page 98: ...RC transmission in HDLC mode set bit 0B3h 6 This is needed for H 324 applications Frame Abortion Frame Idle and Time Fill Frame abortion prematurely finishes transmission of a frame This occurs by sending at least seven consecutive ones with no zero insertion This abort pattern terminates a frame immediately and does not require a FCS or an ending flag An abort pattern followed by a minimum of eig...

Page 99: ... times after FLAGS is set by the MDP Abort Idle Sequence Transmission and Reception An abort idle sequence can be sent by the host setting the MHLD bit 07h 0 The MDP stops sending any normal frame transmission as well as continuous flag transmission and sends continuous ones To stop sending continuous ones the host must reset MHLD Then if no new data is loaded into TBUFFER the MDP sends continuous...

Page 100: ...it timing 5 3 1 Transmitter Example Tx FIFO Disabled The steps to perform a typical HDLC transmission with the Transmitter FIFO disabled are Figure 5 2a 1 Set the MDP configuration in CONF reset the ASYN and FIFOEN bits set the HDLC TPDM and RTS bits 2 The MDP starts transmitting flags immediately and continues with flags until the first byte of data is loaded into TBUFFER 3 Wait for TDBE 1 then p...

Page 101: ...indicates that RBUFFER was loaded with new data before the host read the old data SYNCD indicates that the MDP is receiving flags RBUFFER 7E PE indicates that the FCS had an incorrect CRC FE indicates that an abort idle sequence is detected RBUFFER FF and the frame that was aborted is invalid The MDP does not set the PE bit in this case since no FCS checking is done 3 If NEWS 0 and RDBF 1 or RXFNF...

Page 102: ...times to load new data into TBUFFER 5 CRCS is set as soon as the last bit of the last data byte is sent and prior to sending the first bit of the CRC sequence As soon as FLAGS is set a new data byte of the next frame can be loaded 6 CRCS is reset and FLAGS is set when the last bit of the CRC sequence is sent 7 If MHLD is set anytime during the data CRC or flag transmission the byte transmitted is ...

Page 103: ...ration change implemented receive buffer full transmit buffer empty and memory access also maskable in DSP RAM Each source is individually maskable Table 6 1 identifies the interrupt sources and describes the interrupt clearing procedures 6 2 AUTO DIAL PROCEDURE The host auto dial procedure is the same as outputting data to be transmitted using TBUFFER Figure 6 1 The MDP timing accounts for the DT...

Page 104: ...ioned from a 1 to a 0 Host writes a 0 into NCIE Clears NCIA to a 0 TDBIA TDBIE TDBE TBUFFER is empty and can be written TDBE transitioned from a 1 to a 0 Host writes to BUFFER 10h 7 0 Clears TDBE and TDBIA to 0 RDBIA RDBIE RDBF RBUFFER is full and can be read RDBF transitioned from a 0 to a 1 Host reads RBUFFER 00h 7 0 Clears RDBF and RDBIA to 0 Table 6 2 Auto Dial Default Values Parameter Default...

Page 105: ...l Digits Tone Pairs Hex Dial Digit Tone 1 Tone 2 Tone Pairs 1 RA 07 1 ACTIVATE OHRC 0 RTS 08 0 START 81h CONF 12 0 7 1 NEWC 1F 0 DELAY AT LEAST 4 MS 1 TONES DTMF 09 5 0 PULSES DTMF 09 5 1 NEWC 1F 0 WRITE FIRST DIGIT TO TBUFFER 10 0 7 TDBE 1E 3 1 TDBE 1E 3 1 LAST DIGIT REQ D CONFIGURATION CONF 12 0 7 1 NEWC 1F 0 STOP N Y WRITE DIGIT IN TBUFFER 10 0 7 N N Y 1026F3 2 Auto NOTE Calling tone is continu...

Page 106: ...TO 0 DATA 1 V 23 1650 Hz and FSK allowed ANS over ANS detected for Qualify_Answer length of time AUTO 0 DATA 1 V 32 AC only detected Monitor Signals AUTO 0 DATA 1 V 21 AUTO 0 DATA 1 V 23 1650 Hz and FSK allowed 1300 Hz and FSK allowed AUTO 0 DATA 1 V 22 bis 155 ms of USB1 and ANS 800 ms AUTO 0 DATA 1 V 32 AC only detected 1300 Hz and FSK allowed 155 ms of USB1 and ANS 800 ms DATA 1 CONF 84h 1061F3...

Page 107: ... 32 AA Monitor S1 SB1 and 1270 Hz Start Timer Tb 1000 ms Send AC Monitor V 32 AA AUTO 0 DATA 1 V 32 S1 or SB1 detected AUTO 0 DATA 1 V 23 AUTO 0 DATA 1 V 21 Send 1650 Hz Monitor 980 Hz Start Timer Td 2000 ms Td expired Tc expired and FSK allowed AUTO 0 DATA 1 V 22 bis Tb expired NV25 1 DATA 1 CONF 84H CONF Original CONF DATA 1 CONF A0h StoneB 980 Hz 1061F3 4 Answer AUTO 0 DATA 1 V 8 V 32 AA detect...

Page 108: ...bit 1Eh 3 ignore the read value When bit 1Eh 3 is reset or 5 ms has expired the information is cleared and the DSP self test is performed If the register 10 is not read by the host bit 1Eh 3 will not be reset 6 4 2 DSP Self Test Upon completion of DSP self test the following test results and configuration information is loaded into interface memory and bit 1Eh 3 is set to a 1 Register Function Val...

Page 109: ...ller self test results available for 5 ms Read DSP self test information N Y 1E 3 1 DSP self test results available for 5 ms Read Register 10 to clear 1E 3 and discard value N Y Valid RAM1 and RAM2 checksums in registers 1A 1D Read controller self test information Figure 6 4 Modem Self Test Results Read Procedure ...

Page 110: ...it is set if this final FilteredEQM address 26Fh is larger than the EQMAT threshold address 133h If EQMBaudInterval is 0 then the EQM averaging is disabled as is by default Suitable values for addresses 26Bh and 26Ch are 20h and 64h respectively They may be altered as desired The value obtained at address 26Fh is the same as if the host were to read and average the MSB of EQM read at address 20Ch ...

Page 111: ...m at what speed to operate The status bits will change as mentioned above and the CTS bit will be set to a 1 when the retrain sequence is completed See the RREN bit description in Table 3 1 for rate change procedures in K56flex V 34 V 32 bis modes using a rate renegotiation rather than a retrain Also see the SRCEN bit description in Table 3 1 for rate change procedures in V 34 mode using the secon...

Page 112: ...is now only one method to initiate the Cleardown The retrain method that has been provided in V 32bis is not supported in V 34 The method used is 1 The host loads CONF with C0h 2 The host sets RREN to 1 3 The data pump transmits Cleardown request as per 11 7 of ITU T Recommendation V 34 Receiving a V 34 Cleardown Request 1 On receiving a Cleardown request the MDP responds by writing 96h into the A...

Page 113: ...a 025 in grid Connect each grid to other grids on the same side at several points and to grids on the opposite side through the board at several points Connect all MDP DGND and AGND pins to the ground grid b In a 4 layer design provide a ground plane covering the entire board Connect all MDP DGND and AGND pins to the ground plane at a single point 2 As a general rule route digital signals on the c...

Page 114: ...ource Neutral Noise Sensitive MDP VDD AVDD 23 37 50 79 107 137 138 140 144 Pin TQFP GND DGND AGND 14 18 19 21 31 49 51 52 60 84 85 109 121 132 133 Crystal 141 143 Control 32 72 86 Line Interface 13 20 22 24 25 26 27 28 33 61 78 112 127 128 139 Speaker Interface 29 30 34 Serial LED Interface 71 76 77 108 111 134 Host Interface 1 3 4 6 8 9 12 64 69 144 130 MDP Interconnect 41 47 54 59 73 87 88 89 90...

Page 115: ...ed from each other 5 Provide a good ground plane or grid In some cases a multilayer board may be required with full layers for ground and power distribution 6 Eliminate ground loops which are unexpected current return paths to the power source 7 Locate high frequency circuits in a separate area to minimize capacitive coupling to other circuits 8 Locate cables and connectors so as to avoid coupling...

Page 116: ...und for each of these functions should be separate islands connected together at the power and ground source points only 2 Do not place ground or voltage planes beneath the telephone line side of the Tip and Ring chokes 3 Decouple power from ground with decoupling capacitors as close to the MDP device power pins as possible 4 Decouple the power cord at the power cord interface with decoupling capa...

Page 117: ...esonant Load Capacitance C L 18 pF nom 18 pF nom Shunt Capacitance C O 7 pF max 7 pF max Series Resistance R 1 35 Ω max 20 nW drive level 80 Ω max 20 nW drive level Drive Level 100µW correlation 500µW max 100µW correlation 300µW max Operating Temperature 0 C to 70 C 0 C to 70 C Storage Temperature 40 C to 85 C 40 C to 85 C Mechanical Dimensions L x W x H 11 05 x 4 65 x 13 46 mm max 7 5 x 5 2 x 1 3...

Page 118: ...P are shown Figure 7 1 144 pin TQFP A typical external circuit for connection to the line with no external hybrid and a transmit level to 7 dBm is shown in Figure 7 2 A typical external circuits for connection to the line with an external hybrid and a transmit level to 0 dBm is shown in Figure 7 3 A typical external speaker circuit is shown in Figure 7 4 ...

Page 119: ...CLKOUT SR3OUT SR3IN SA2CLK SR2CLK SR2IO VCNTRLSIN VSCLK VSTROBE VRXOUT VTXSIN VCLKIN 43 44 46 47 45 42 106 94 93 89 87 91 88 90 103 73 104 58 55 53 54 56 57 SLEEPO IASLEEP 113 59 10 0 1 CER VREF 27 10 0 1 CER VC 28 96 62 124 95 98 97 99 100 92 38 39 72 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED WKDRES TIRO2 VTH2 VDD 10K VDD 10K 74 140 AVDD AV...

Page 120: ... 2N2222 Q2 2N2102 D1 HLL5243B D2 D5 1N4003 VR1 V150LA10A NOTES 1 CHOOSE R1 VALUE TO OBTAIN 600 OHM INTERNAL IMPEDANCE 2 CHOOSE R2 AND R3 VALUE TO OBTAIN A 6 DB LOSS FROM TIP AND RING TO RIN 1061F7 3 LIU R3 NOTE 2 Figure 7 2 Typical Line Interface A A A A 470 pF 68 1K 0 1 uF 1458 137K RXA RIN TXA2 TXA1 44 2K 44 2K 44 2K V 01 1458 01 44 2K V 604 TXA 1061F7 4 Ext HyB WL 7 6 5 8 2 3 1 4 A B Figure 7 3...

Page 121: ...6DPFL SP RCV56DPFL SP and RCV336DPFL SP Designer s Guide 1119 7 9 A A A 50 OHM SPEAKER 220 LM386 750 10 V 0 1 uF 0 1 1K SPKM 4 8 3 7 2 6 1 5 0 1 1061F7 5 Sch Spkr _ Figure 7 4 Typical External Speaker Circuit ...

Page 122: ...EF 0 50 BSC 0 27 0 17 0 08 MAX 0 0020 0 8563 0 0197 0 0067 0 0043 A A1 A2 D D1 D2 L L1 e b c Coplanarity Min Max Min Max Inches Dim Ref 144 PIN TQFP GP00 D252 Metric values millimeters should be used for PCB layout English values inches are converted from metric values and may include round off errors 0 0630 MAX 0 0059 0 0551 REF 0 8760 0 7874 REF 0 6890 REF 0 0295 0 0394 REF 0 0197 BSC 0 0106 0 0...

Page 123: ...cedure consists of the following handshake The answering fax machine sends an identification signal and the originating machine responds with a command signal A training check is sent at a high speed and the receiving machine informs the transmitting machine if the training check was successful This usually occurs at V 21 300 bps Frequency Shift Keying FSK modulation in HDLC format HDLC stands for...

Page 124: ... the phase C format 8 1 4 Phase D The post message phase D procedure uses FSK and HDLC format The calling station will typically send an End Of Message EOM signal This FCF command EOM informs the called station that this is the end of the page and return to Phase B A Multi Page Signaling MPS or End Of Procedure EOP signal may be sent instead of EOM The MPS signal informs the called unit that there...

Page 125: ...14400 bps therefore the host microprocessor may not be able to keep up if implementing HDLC without the use of a serial I O device DOCUMENT PHOTOELECTRIC CONVERSION T E L E P H O N E L I N E 1026F8 01 Basic DATA COMPRESSION MODULATOR DEMODULATOR DATA DECODING TX SCANNING CONTROL PRINTER CONVERSION RX SCANNING CONTROL RECEIVED IMAGE Figure 8 1 Basic Block Diagram of G3 Facsimile ...

Page 126: ... CALLING TONE 1100 Hz 0 5S ON 3S OFF CALLING TONE INDICATE NON SPEECH TERMINAL CALLED STATION ID 2100 Hz 2 6S ON 4S TRANSMITS DOCUMENT END OF MESSAGE 300 BPS FSK HDLC FORMAT END OF MESSAGE EOP MPS OR PRI Q MAY BE SENT MESSAGE CONFIRMATION 300 BPS HDLC FORMAT MESSAGE CONFIRMATION POST MESSAGE RESPONSE OF MESSAGE CONFIRMATION RTP RTN PIP OR PIN MAY MESSAGE CONFIRMATION BE SENT PHASE A PHASE B PHASE ...

Page 127: ... TIME OUT THE CONNECTION ATTEMPT 1 SEND 1100 Hz CNG TONE DETECT 2100 Hz CED TONE ATV25 0B 4 1 YES NO NOTE IF CED TONE IS DETECTED WAIT NOTE UNTIL CED TONE TURNS OFF BEFORE NOTE NEXT STATE RECEIVE DIS FRAME SEND DCS FRAME SEND TCF SIGNALS RECEIVE CFR OR FTT FRAMES TRANSMIT MESSAGE MESS SEND EOM FRAME RECEIVE MCF FRAME EXIT 1026F8 03 Orig TURN OFF CALLING TONE Figure 8 3 Originating a Fax Call Gener...

Page 128: ...ON 81h CONF 12 0 7 1 DTMF 9 5 1 ORG 9 4 1 NEWC 1F 0 SET CALLING TONE OFF TIME FOR 3 SECONDS WRITE TO RAM METHOD 2 012Ch 2DA 291 RETURN TDBE 1E 3 1 NO SEND 1100 Hz CNG TONE LOAD 1100 Hz TONE 11h TBUFFER 10 0 7 RETURN YES YES 1026F8 04 Orig A SET CALLING TONE DURATION FOR 500 MS DEFAULT WRITE TO RAM METHOD 2 0032h 2D9 290 Figure 8 4 Originating a Fax Call Phase A ...

Page 129: ...OTE TRANSMITTED IS THE DCS FRAME SEND TCF SIGNALS HIGH SPEED CONFIGURATION SET UP 1 5 SECOND TIMER 1 RTS 8 0 LOAD ZEROES INTO TRANSMIT BUFFER 00h TBUFFER 10 0 7 YES ABORT TIMER EXPIRED NO RECEIVE CFR OR FTT FRAMES RECEIVE FSK HDLC SIGNALS CFR DETECTED YES FTT DETECTED ABORT RETURN SEND DCS FRAME YES YES NO NO NOTE DATA TO BE RECEIVED NOTE SHOULD BE A CFR OR FTT FRAME 1026F8 05 Orig B 0 RTS 8 0 RET...

Page 130: ...36DPFL SP Designer s Guide 8 8 1119 TDBE 1 NO TRANSMIT MESS HIGH SPEED CONFIGURATION 1 RTS 8 0 YES LOAD DATA INTO TRANSMIT BUFFER XXh TBUFFER 10 0 7 MORE TO TRANSMIT RETURN NO YES 1026F8 06 Orig C Figure 8 6 Originating a Fax Call Phase C ...

Page 131: ...D EOM FRAME TRANSMIT FSK HDLC SIGNALS RETURN 1026F8 07 Orig D RECEIVE MCF FRAME RECEIVE FSK HDLC SIGNALS RETURN NOTE THE FRAME TO BE LOADED NOTE AND TRANSMITTED IS THE NOTE EOM FRAME NOTE DATA TO BE RECEIVED NOTE SHOULD BE AN MCF FRAME Figure 8 7 Originating a Fax Call Phase D ...

Page 132: ...S ESTABLISHED RLSD TURNS ON YES NO DATA ANSWER CONNECT 1 YES EXIT DATA CONNECTION FAILED DATA CONNECTION ESTABLISHED NO FOR DATA ANSWER PRODEDURE REFER TO FIGURE 7 2 AUTODETECTION RECONFIGURATION ANSWER SEND DIS FRAME 2 RECEIVE DCS FRAME RECEIVE TCF SIGNALS VALID TRAIN NO SEND FTT FRAMES NOTE DIS DCS TCF CFR MESS FTT EOM AND MCF ARE FRAMES SPECIFIED BY CCITT T 30 SPECIFICATION SEND CFR FRAMES RECE...

Page 133: ...3h AA1 FC9Ch AA2 01B4h AA3 C147h AA4 48C6h AA5 BIQUAD 2 01B3h BA1 0097h BA2 01B4h BA3 C147h BA4 4897h BA5 3 NOTE 1100 Hz COEFFICIENTS ARE LISTED IN TABLE 4 2 NO TIME OUT 3 SECONDS DELAY 600 MS YES NO NO TONEA 0 NO DELAY 3 2 SEC YES TONEA 1 NO YES CNG DETECTED NOTE THE DELAYS BETWEEN THE CHECKING OF THE TONEA BIT DETERMINES IF THE TONE DETECTED MEETS THE CADENCE REQUIREMENTS SPECIFIED BY CCITT V 25...

Page 134: ...IGURE TONE MODE FOR 2100 HZ WRITE TO RAM METHOD 2 4AABh 281 280 1 RTS 08 0 WAIT FOR 2 6 TO 4 0 SEC 0 RTS 08 0 RETURN NOTE THE 2100 CALLED TONE IS GENERATED FOR A DURATION OF 2 6 TO 4 0 SECONDS 1026F8 10 Ans A CED FAX ANSWER GENERATE 2100 Hz CED TONE WAIT 75 MS SILENCE RETURN GENERATE 2100 Hz CALLED TONE CED Figure 8 10 Answering a Fax Call Phase A CED ...

Page 135: ...LID TRAIN DETECTED RECEIVE DCS FRAME RECEIVE FSK HDLC SIGNALS RETURN NOTE DATA TO BE RECEIVED SHOULD BE A DCS FRAME SEND CFR FRAMES TRANSMIT FSK HDLC SIGNALS RETURN NOTE THE FRAME TO BE LOADED AND TRANSMITTED IS THE CFR FRAME SEND FTR FRAMES TRANSMIT FSK HDLC SIGNALS RETURN NOTE THE FRAME TO BE LOADED AND TRANSMITTED IS THE FTR FRAME RECEIVE DCS FRAME NOTE THE FLAGDT BIT IN HIGH SPEED FAX MODE WIT...

Page 136: ...FL SP Designer s Guide 8 14 1119 RECEIVE MESS HIGH SPEED CONFIGURATION RLSD 1 NO YES NO RDBF 1 YES READ RECEIVE BUFFER RBUFFER XXh DETECT 6 CONSECUTIVE EOLS NO RLSD 0 YES RETURN YES NO 1026F8 12 Ans C Figure 8 12 Answering a Fax Call Phase C ...

Page 137: ...RAME LOW SPEED CONFIGURATION RETURN NOTE DATA TO BE RECEIVED SHOULD BE A EOM MPS OR PRI Q FRAME RECEIVE FSK HDLC SIGNALS SEND MCF FRAMES TRANSMIT FSK HDLC SIGNALS RETURN NOTE THE FRAME TO BE LOADED AND TRANSMITTED IS THE MCF FRAME 1026F8 13 Ans D Figure 8 13 Answering a Fax Call Phase D ...

Page 138: ...CV336DPFL SP Designer s Guide 8 16 1119 FLAGS 0A 1 1 NO TRANSMIT FSK HDLC SIGNALS LOW SPEED CONFIGURATION TRANSMIT PARALLEL DATA YES TRANSMIT PREAMBLE WAIT 90 MS 0 RTS 08 0 RETURN 1026F8 14 FSK Figure 8 14 Transmitting FSK HDLC Signals ...

Page 139: ... CONFIGURATION CONFIGURE FOR V 21 CHANNEL 2 FSK A8h CONF 12 0 7 1 NEWC 1F 0 SET UP FOR PARALLEL DATA HDLC AND DATA BITS 1 TPDM 08 6 1 HDLC 06 4 1 DATA 09 2 1 NEWC 1F 0 NO NEWC 0 RETURN YES NO NEWC 0 YES 1026F8 15 LS Conf 1 RTS 08 0 TX ONLY Figure 8 15 Low Speed Configuration Routine ...

Page 140: ... and RCV336DPFL SP Designer s Guide 8 18 1119 CTS F 5 1 NO TRANSMIT PREAMBLE 1 RTS 8 0 DELAY 1 SECOND RETURN YES NOTE THE MODEM SENDS 1 SECOND OF HDLC FLAGS 7Eh OR 01111110 1026F8 16 Tx Pream Figure 8 16 Transmit Preamble Routine ...

Page 141: ...TA INITIALIZE BYTE COUNT YES LOAD DATA INTO TRANSMIT BUFFER XXh TBUFFER 10 0 7 MORE TO TRANSMIT RETURN NO YES 1026F8 17 Tx Par Data NOTE COUNT NUMBER OF BYTES IN HDLC FRAME TO BE SENT DECREMENT BYTE COUNT WHEN BYTE COUNT 0 THERE IS NO MORE DATA TO BE TRANSMITTED Figure 8 17 Transmit Parallel Data Routine ...

Page 142: ... 1 NO RECEIVE FSK HDLC SIGNALS YES READ RECEIVE BUFFER RBUFFER 0 0 7 XXh RDBF 1E 0 1 NO SYNCD 0A 0 1 YES YES NO NO RETURN RLSD 0F 7 0 YES NOTE WAIT FOR RLSD 0 TO INDICATE END OF FRAME READ DATA PER HDLC DESCRIPTION IN SECTION 5 1026F8 18 Rx Pream Figure 8 18 Receive FSK HDLC Signals ...

Page 143: ... 17 14400 14h CONF V 29 9600 12h CONF V 29 7200 02h CONF V 27 4800 01h CONF V 27 2400 NEWC 1F 0 1 NEWC 0 NO YES DISABLE HDLC 0 HDLC 06 4 1 DATA 09 2 0 DTR 09 0 NOTE CONFIGURE FOR THE SPEED SPECIFIED BY THE DCS FRAME FROM THE CALLING MODEM RETURN NEWC 1F 0 1 NEWC 0 NO YES 1026F8 19 HS Conf Figure 8 19 High Speed Configuration Routine ...

Page 144: ...ither NULL EOP MPS or EOM The page count followed by the block count followed by the total number of frames in the block are transmitted next The FCS and ending flag are finally transmitted The PPR frame structure also begins with the same Flag Address and Control field The FCF for PPR is the next octet The FIF consists of 256 or 64 bits depending on how many frames were transmitted The contents o...

Page 145: ...ODED INFO NSF FRAME OPTIONAL CSI FRAME OPTIONAL DIGITAL ID FRAME MANDATORY FLAG 01111110 ADDRESS 11111111 CONTROL 1100X000 FCF 8 BIT 8 BIT 8 BIT 8 BIT FIF 32 BIT FCS 16 BIT 8 BIT FLAG 01111110 FCS FRAME CHECK SEQUENCE CCITT V 41 CRC 16 IS USED 1026F8 20 HDLC Figure 8 20 HDLC Frame Structure ...

Page 146: ...rmt RETURN TO CONTROL RTC INDICATING END OF DOCUMENT TRANSMISSION FORMAT SIX CONSECUTIVE EOLS DATA EOL DATA EOL DATA FILL EOL START OF PHASE C T T T DATA EOL END OF PHASE C RTC EOL EOL EOL EOL EOL EOL T MINIMUM TRANSMISSION TIME OF A TOTAL CODED SCAN LINE EOL DATA Figure 8 21 Phase C Format ...

Page 147: ...ATA FACSIMILE CODED DATA BLOCK FCD AFTER 256 FRAMES TRANSMIT 3 TIMES FLAG ADDRESS FIELD CONTROL FIELD FCF FOR FCD FRAME NUMBER FACSIMILE DATA EOL TAG ALIGN BITS FCS CHECK FLAG OR 64 FCF FOR RCP FCS FLAG ACS ADDRESS FIELD CCS CONTROL FIELD FCS FRAME CHECK SEQUENCE AFTER THIRD RCP TRANSMIT 50 MS MAX OF FLAGS RCP BLOCK 1026F8 22 ECM Frm Figure 8 22 ECM Frame Structure ...

Page 148: ...IN LAST MESSAGE RX READY MESSAGE PAGE 1 BLOCK 0 PPS EOP INDICATES END OF PROCEDURE I E NO MORE PAGES TO TRANSMIT PPR INDICATES FRAME ERRORS RETRANSMIT MESSAGE FRAMES IN ERROR PAGE 1 BLOCK 0 PPS EOP PPR 4TH REQUEST FOR RETRANSMISSION OF FRAMES IN ERROR FOR PAGE 1 BLOCK 0 AFTER 4TH REQUEST FOR RETRANSMISSION OF ERRORED FRAMES ON THE SAME BLOCK THE TRANSMITTER MAY RESPOND WITH EOR EOP INDICATES END O...

Page 149: ...PR FCS F FIF PPS NUL EOP MPS EOM PAGE COUNT 0 255 BLOCK COUNT 0 255 TOTAL OF FRAMES IN BLOCK 1 256 FSK 300 BPS FCS FLAG ACS ADDRESS FIELD CCS CONTROL FIELD FCS FRAME CHECK SEQUENCE PPR FRAME STRUCTURE FCF FOR PPR 256 BITS BITS PER FRAME 0 CORRECT 1 INCORRECT 1026F8 24 PPS Figure 8 24 PPS and PPR Frame Structure ...

Page 150: ...ECTED RECONFIGURE TO FSK HIGH SPEED CONFIGURATION NO FED 0F 6 1 YES YES INITIALIZE AND START TIMER1 HIGH SPEED DETECTED T 30 TIMEOUT ERROR TIMER1 6 7 SEC PNSUC 0A 7 1 NO YES NO YES NO FLAGDT 0A 6 1 YES PNSUC 0A 7 1 TIMER2 100 MS NO YES TIMER1 6 7 SECOND ESCAPE TIMER 6 7 SEC TIMER2 SYNCD DEBOUNCE TIMER 100 TO 200 MS Figure 8 25 FSK Signal Recognition Algorithm ...

Page 151: ...is detected When JM is detected the current CM octet is completed and then CJ gets appended to the transmitted data stream A 75 ms silence period follows CJ transmission and the CONF register is updated to the Modulation Mode indexed by the highest common modulation mode in JM Table 9 3 If no modulation modes are common the CONF register changes to AFh the V 8 Cleardown mode 9 1 2 Originating With...

Page 152: ...f the received CM contained a GSTN octet The GSTN octet will be sent indicating cellular access if control bit 305h 2 is set Table 9 1 V 8 Host Control Bits Address Hex 7 6 5 4 3 2 1 0 Default Value Hex 1 304 Call Function to be Transmitted Send GSTN Octet No K56 PN ID with ANSam Transmit CI No TX of ANSam until CI Detected C0 305 Protocol Bits to be Transmitted No RLSD in V 8 Cellular Access Send...

Page 153: ...3 half duplex A4 314 V 21 A0 Notes 1 See CONF codes in Table 3 1 2 Default value assumes V 23 answer mode change to A1 for V 23 originate mode see CONF bits in Table 3 1 Table 9 4 CM Frame Address Hex Octet Default Value Hex Preamble FF 32D SYNC CM E0 32E Data Call Function C1 32F modulation 0 40 330 modulation 1 13 331 modulation 2 94 332 Protocol optional 1A 333 GSTN optional 2D 334 Frame End 7E...

Page 154: ...llowed CF 0 Allowed 40 9 3 V 8 AND AUTOMODE The MDP offers an automode option for connecting to the large existing base of non V 34 modems By setting AUTO 1 and DATA 0 from the V 8 configuration CONF AA the V 32 bis automode method of automoding will be performed as well as the V 8 method Table 9 8 Table 9 8 Automode Parameters CONF AUTO DATA Result 7Xh V 32 bis V 32 modes 1 0 Automodes from V 32 ...

Page 155: ...e NEWS masks for these locations are 370h and 371h respectively For a full description refer to Section 4 Table 9 9 Receiver Handshake Phase and States Register Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16 SECRXB Receiver Handshake Phase Receiver Handshake Phase State Bits 7 5 Receiver Handshake Phase Bit 7 Bit 6 Bit 5 Dec Value Handshake Phase ITU Specification 0 0 0 0 Phase 1 V 8 0 0 1...

Page 156: ... 3 V 34 0 1 1 3 Phase 4 V 34 1 0 0 4 Phase 4 Rate Renegotiation V 34 Bits 4 0 Transmitter Handshake Phase State Phase 1 Transmitter Handshake Phase 1 States Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 State Number Originate Mode Transmitter State Answer Mode Transmitter State 0 0 0 0 0 00 Pausing 400 ms Transmitting silence Sending ANSam 0 0 0 0 1 01 Sending CI Sending JM 0 0 0 1 0 02 Sending Silence 500 ms or ...

Page 157: ...V336DPFL SP Designer s Guide 1119 9 7 The phase state value is shown above or below the signal trace Figure 9 1 Phase 2 Receiver States The phase state value is shown above or below the signal trace Figure 9 2 Phase 2 Transmitter States ...

Page 158: ... SP and RCV336DPFL SP Designer s Guide 9 8 1119 The phase state value is shown above or below the signal trace Figure 9 3 Phase 3 States The phase state value is shown above or below the signal trace Figure 9 4 Phase 4 States ...

Page 159: ...00 23 5 33 CRd 1529 2225 10 1900 10 34 ESr 1529 2225 10 1650 10 38 1529 2225 10 650 10 3A 1529 2225 10 400 10 Notes The 1650 Hz and 980 Hz single tones are V 21 MARK frequencies for the high and low channels respectively Therefore it would be generated by setting DTR immediately after writing 34h or 24h into TBUFFER If in answer mode set NV25 1 to prevent answer tone from being sent instead of MAR...

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Page 161: ...er bits sample rate for minimum storage requirements The Rx coder writes 16 bit coded words to output register VBUFR then sets status bit RDBF The IRQ output may be enabled using the RDBIE bit to interrupt the host whenever the RDBF bit sets to indicate that VBUFR is full Receive FIFO Operation The receiver FIFO is always enabled similar to data mode to allow reading in bursts if desired Always re...

Page 162: ...0h 81h 83h or 86h Digital Input Scaling 1026F10 1 Rx BD Tone Detectors DTMF Receiver Host Programmable Sample Rate 16 bit Coded Word Rx Coder Output VBUFR Receiver Analog Input RXA Analog to Digital Converter ADC ADPCM Rx Coder Figure 11 1 ADPCM Rx Coder ADPCM Tx Decoder Digital Output Scaling Digital to Analog Converter DAC 16 bit Coded Word Tx Decoder Input VBUFT Host Programmable Sample Rate Tr...

Page 163: ... CDEN X CODBITS 1 RXV 0 TXV 1 NEWC NEWC 0 No Yes No Yes Read high byte from VBUFR DONE 0 TXSQ 0 CDEN 1 CEQ 0 RXV 1 NEWC No Yes NEWC 0 End NOTE Reset CDEN 0 for 16 bit pass through voice mode RDBF 1 No Yes SYNCD and PE 1 No Yes Read low byte from VBUFR No Yes FE 1 RDBF 1 Bypass this step for pass through mode Figure 11 3 Rx Coder Operation ...

Page 164: ...V 1 CEQ 1 NEWC No Yes NEWC 0 End 1 TPDM Enable Transmit FIFO if desired 1 FIFOEN NOTE Reset DCDEN 0 for 16 bit pass through voice mode 0 TEOF Write first low byte to VBUFT SECTXB if FIFO 0 TXFNF 1 No Yes 1 TEOF Write first high byte to VBUFT No Yes TXFNF 1 Write low byte to VBUFT SECTXB if FIFO 0 Write high byte to VBUFT NOTE These steps are not required in Voice Pass through Mode Figure 11 4 Tx D...

Page 165: ...orresponding to a recorded level of nearly 16 dBm By lowering VAGCREF the recorded volume is lowered Slew Rate VSRATE The slew rate parameter controls the rate at which the gain tracks the input signal The larger the slew rate multiplier the faster the AGC Gain word tracks the input signal The VoiceSlewRateCtr is used to allow the AGC gain word to quickly adjust to the input level at the beginning...

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Page 167: ...r Enable Disable V8bDetEn 1 Enable V 8bis detector 0 Disable V 8bis detector AudioSpan Control Register 2 Address 400h Bit 7 Half Duplex Gain Control Enable Disable HDXgcEn 1 Enable half duplex gain control Recommended for mic spkr operation or when handset echo canceller is used 0 Disable half duplex gain control Bit 6 Mic AGC Enable Disable QmicAGCen 1 Enable AGC on mic Not recommended for heads...

Page 168: ...uld be set when the audio link is in an on hook state When the handset is picked up or the mic is enabled the host should reset bit 400h 2 This will cause bit 419h 7 to reset on the remote modem indicating an audio link request 12 1 4 Generating Ring and Ringback A dual tone generator is available during a ML144 AudioSpan connection When enabled the AudioSpan audio is suppressed and the tone s is ...

Page 169: ...e values in address 42Ah are used to generate the Tx Rate sequence words 2 and 3 The ARC bit must be set 1 to allow the modems to negotiate the highest common voice data rate to be used AudioSpan Rate Sequence Word 2 and Word 3 are stored in RAM and are set up from contents of address 42Ah after NEWC is set They can be changed directly by the host without using masking registers after DTR is set T...

Page 170: ...2Eh gives the user more flexibility Changing CONF and setting RREN will change the data only rate for when silence detection is being used The voice data rate will not be affected 12 1 7 Maximum Voice Data Rate The voice data rate is defined as the user data rate when audio information is being sent Assuming minimal line disturbances the maximum voice data rate is 14 4k bps in ML144 however a degr...

Page 171: ...er a RREN and is adjustable only when the modems are connected The speaker volume is relative to the microphone gain of the remote audio source Values written to address 990h do not correspond to absolute output levels but rather to relative changes in output level The following table illustrates the relative gain in 2 dB steps Speaker Relative Gain dB Value in 990 Hex 10 FC00 maximum 8 FA00 6 F80...

Page 172: ...yyyyyyyyyyy y bits 0 A and x bits B F M 1 is calculated based on the current gain value M 2 is calculated based on the new gain value 12 1 11 TELIN TELOUT Gain Control When using TELIN TELOUT for handset operation the gain control has to be through address B7Eh for TELIN and address 990h for TELOUT The VOLUME bits and mic gain control at address 3D3h do not apply 12 1 12 Handset Echo Canceller Whe...

Page 173: ...ts to 2 To Select Handset 1 Turn on handset mode Set bit 400h 5 to 1 2 Turn off the AGC Reset bit 400h 6 to 0 3 Enable the half duplex gain control Set bit 400h 7 to 1 4 Turn on the handset echo canceller after connected Writing 8004h to A5Ch 5 Adjust volume as desired Use speaker scale location 990h default F000h Note that this location may get reset after RRENs or RTRNs Note VOLUME bits do not a...

Page 174: ...er words ring and ringback tones should not be generated again until after both modems have been in a terminated audio link state Ring or No Ring Some applications may require the audio link always be enabled with no control from the modem particularly in headset operation In this case bit 400h 2 should not be set and since 400h 2 is not set and therefore 419h 7 is not set on either modem no ring ...

Page 175: ...ed to come from TELIN and the output to the voice IA is sent to TELOUT 13 1 1 DTMF and Dual Tone Modes DTMF dialing can be sent to the line DTMF 1 and or to the speaker SpDTMF 1 see Table 13 1 The dial digit is sent by writing to TBUFFER similar to how it is done in mode 81h To send a DTMF digit write its number into TBUFFER For example to send the DTMF digit 4 to both the line and the speaker set...

Page 176: ...ic and MuteSp control the muting of the microphone and the speaker respectively To be more precise the MuteSp bit mutes the line input MMicLVL and VMicLVL control the modem and voice microphone input levels respectively 13 2 VOICE PATHS The following describes how to setup the voice mode paths The Integrated Analog IA function has a dual interface a Modem IA and a Voice IA The voice transmit and r...

Page 177: ...ITS SP06 1 0 SDCDE SP02 3 Silence Insertion TXOUTPUT DCDEN SP02 5 0 TBUFFER SP17 Data FROM Host 0L 0H 1L 1H 2L 2H 3L 3H RBUFFER SP16 Data TO Host Transmit Scaling TSCALE TFSCALE X 2 Bits 00 3 Bits 01 4 Bits 1X Silence Deletion 2 Bits 00 3 Bits 01 4 Bits 1X Voice AGC 1 0 ENCODE BITS SP02 1 0 SCDE SP02 3 ADCSCL X RXIN 2 1 1 0 0 1 0 1 1 1 0 0 1 Figure 13 1 Voice Flow Block Diagram ...

Page 178: ..._V 11 VSpkOut 3E0 1 0 10 Squelch 00 0 dB 10 6 dB 01 12 dB 11 VOLUME SP01 7 6 VSpkDisable 3E1 0 SPK_V MIC_M 10 RIN 01 11 00 MLinOut 3E0 7 6 MLinDisable 3E1 3 TXA1 TXA2 RIN 00 MIC_M 11 MSpkOut 3E0 5 4 10 Squelch 00 0 dB 10 6 dB 01 12 dB 11 MSpkDisable 3E1 2 SPK_M SR3OB SR4OB MODEM 10488 IA VOICE 10488 IA VOLUME SP01 7 6 Figure 13 2 Transmit Voice Paths ...

Page 179: ...1 0 SR4IB SR3IB RXIN MODEM 10488 IA 0 dB 00 10 dB 01 15 dB 10 20 dB 11 MIC_M RIN RecPath 3E1 4 1 RecPath 3E1 5 1 Voice Mic Gain SP13 1 0 0 dB 00 10 dB 01 15 dB 10 20 dB 11 MIC_V TELIN RecPath 3E1 6 1 RecPath 3E1 7 1 VOICE 10488 IA RecPath 43E 0 0 RecPath 43E 0 1 Figure 13 3 Receiver Voice Paths ...

Page 180: ...Spkr Output Bits 7 6 Modem IA Line Output 00 SR4OB to TXA1 TXA2 01 RIN to TXA1 TXA2 10 MICM to TXA1 TXA2 11 RIN to TXA1 TXA2 Bits 5 4 Modem IA Speaker Output 00 RIN to SPKM 10 SR4OB to SPKM 11 MICM to SPKM Bits 3 2 Voice IA Line Output 00 SR3OB to TELOUT 01 TELIN to TELOUT 10 MICV to TELOUT 11 TELIN to TELOUT Bits 1 0 Voice IA Speaker Output 00 TELIN to SPKV 10 SR3OB to SPKV 11 MICV to SPKV ...

Page 181: ...able the Modem Mic Input MICM EnMMIC 1 Enable MICM input 0 Disable MICM input Bit 4 Enable the Modem Line Input RIN EnRIN 1 Enable RIN input 0 Disable RIN input Bit 3 Disable the Modem Line Output TXA2 MLinDis 1 Disable TXA2 output 0 Enable TXA2 output Bit 2 Disable the Modem Speaker Output SPKM MSpkDis 1 Disable SPKM output 0 Enable SPKM output Bit 1 Disable the Voice Line Output TELOUT VLinDis 1...

Page 182: ...osed to the analog or IA loopback features described above in the Line Output and Speaker Output sections Sidetone can be used for a music on hold mode For example the receive voice samples can be taken from the MDP microphone input MICM and then played out over the MDP line out TXA1 TXA2 The sidetone feature can be used in conjunction with recording Addresses B6Bh and B69h control the amount of l...

Page 183: ... Audio Sampling Frequency 11025 Hz To enable business audio set bit 43Eh 7 This bit takes effect at NEWC when CONF ACh RXV and or TXV must also be set 13 3 VOICE AGC See Section 11 3 13 4 SPEAKERPHONE CONVERSTATION RECORD When in speakerphone mode the conversation may be recorded by enabling variable gains on both the transmit and receive paths and reading samples from RBUFFER just as in voice pas...

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Page 185: ...the client modem will be in an originate handshake mode sending its half duplex TRN second The same handshake sequence will occur regardless of who originated the call i e the ORG bit does not influence the handshake sequence which takes place after V 8 The server modem will typically always answer calls while the client modem will usually originate them In the event a server modem must use a call...

Page 186: ...12000 40000 6 14400 42000 7 16800 44000 8 19200 46000 9 21600 48000 A 24000 50000 B 26400 52000 C 28800 54000 D 31200 56000 E 33600 Reserved Table 14 2 K56flex Data Rate Versus Speed Bit Values SPEED Hex Data Rate bps SPEED Hex Data Rate bps 0 0 300 10 33600 1 600 11 32000 2 1200 12 34000 3 2400 13 36000 4 4800 14 38000 5 9600 15 40000 6 12000 16 42000 7 14400 17 44000 8 7200 18 46000 9 16800 19 4...

Page 187: ...ersion number is an ASCII number received during INFO0 which may be used to identify the remote modem type The code revision number is always odd for server modem and even for client modem 409h Desired K56flex Receive Speed See Table 14 1 604h Maximum Receive Rate Mask See Table 14 1 605h Maximum Transmit Rate Mask See Table 14 1 The NEWC bit should be set after control bits have been setup as des...

Page 188: ...o a lower modulation mode as needed if the AUTO bit is set If a client modem calls another client modem setup to answer as a K56flex modem the connection will automatically fall back to V 34 The same is true if the modems are not both setup for A law or µ law or if the line probe has determined that K56flex cannot be supported over the selected line 14 1 6 EQM Readings The EQM readings and interpr...

Page 189: ... get near end 9 Quickly read approximately 64 samples to get a good average of EQM at 20Ch 16 bit reads and obtain average 10 Select SPEED from Table 14 4 Note In step 10 33 6k value of 0Eh should only be selected if the symbol rate is 3429 If the average EQM is very good yet the symbol rate is only 3200 then a maximum of 31 2k should be selected value of 0Dh If the symbol rate is 3000 then a maxi...

Page 190: ... 3000 28800 0110 01C2 00EC 0147 0C 26400 01C3 034F 0148 02BF 0B 24000 0350 05E0 02C0 0550 0A 21600 05E1 0A00 0551 0900 09 19200 0A01 0EA0 0901 0F00 08 16800 0EA1 1700 0F01 1800 07 14400 1701 2400 1801 2500 06 12000 2401 2E00 2501 2F00 05 14 3 CHANGES TO RAM ADDRESSES Some previously defined RAM locations were changed to optimize internal RAM usage The addresses affected are those above CXX all are...

Page 191: ...RCVDL56DPFL SP RCV56DPFL SP and RCV336DPFL SP Designer s Guide 1119 15 1 15 RCV56DPFL SP DOWNLOADING To be added ...

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Page 193: ...INSIDE BACK COVER NOTES ...

Page 194: ... 773 3907 US Northeast Office Rockwell Semiconductor Systems 239 Littleton Road Suite 4A Westford MA 01886 Phone 508 692 7660 Fax 508 692 8185 Australia Rockwell Semiconductor Systems Rockwell Australia Limited 3 Thomas Holt Drive P O Box 165 North Ryde NSW 2113 Australia Phone 61 2 805 5555 Fax 61 2 805 5599 Europe Mediterranean Rockwell Semiconductor Systems c o Rockwell Automation S r l Via Di ...

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