RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide
8-20
1119
RLSD (0F:7) = 1?
NO
RECEIVE
FSK/HDLC
SIGNALS
YES
READ RECEIVE BUFFER
RBUFFER (0:0-7)
→
XXh
RDBF (1E:0) = 1?
NO
SYNCD (0A:0) = 1?
YES
YES
NO
NO
RETURN
RLSD (0F:7) = 0?
YES
NOTE: WAIT FOR RLSD = 0
TO INDICATE END OF FRAME.
READ DATA PER HDLC
DESCRIPTION IN
SECTION 5
1026F8-18 Rx Pream
Figure 8-18. Receive FSK/HDLC Signals
Summary of Contents for RC336DPFL
Page 193: ...INSIDE BACK COVER NOTES ...