RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide
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Function 70: V.21/V.23 CTS Mark Qualify
Acc Method: 1
Address: 10Dh:3
In V.21/V.23 configurations, CTS turn-on qualifying time can be controlled by writing to bit 10Dh:3 [0 = no qualifying time
after Mark (default); 1 = qualifying time of 45 ±5 ms after Mark]. This bit is unaffected by the action of NEWC.
Function 71-72: Not Applicable
Function 73:
No Automode to FSK
Acc Method: 1
Address: 13Fh:0
Automode to FSK modes can be controlled by writing to bit 13Fh:0 [0 = automode to FSK enabled (default); 1 = automode to
FSK disabled). This bit remains unaffected by NEWC.
If enabled (0), the automode selection will allow FSK connections. If disabled (1), automode selection will not configure to
any FSK mode.
Function 74:
Receive FIFO Trigger Level
Acc Method: 1
Address: 32Ch
Transmit FIFO Extension Enable
Acc Method: 1
Address: 702h:0
Receive FIFO Extension Enable
Acc Method: 1
Address: 701h:0
Transmitter FIFO (TXFIFO)
The 16-byte TXFIFO is controlled by writing to the FIFOEN bit (04h:4) [0 = TXFIFO disabled; 1 = TXFIFO enabled].
The 128-byte TXFIFO Extension (TXFIFOX) is controlled by writing to the Transmit FIFO Extension Enable bit (702h:0)
[0 = TXFIFOX disabled; 1 = TXFIFOX enabled (default)].
When the TXFIFO is enabled (FIFOEN = 1), the host can continuously write to TBUFFER as long as TXFNF status bit
(0Dh:1) is set. The TDBE bit (1Eh:3) will be set whenever the TXFIFO is empty (TXFIFIX disabled) or when the TXFIFO can
accept more bytes (TXFIFOX enabled). Two control bits, TEOF (11h:1) and TXP (11h:0) are buffered along with the TXFIFO
data. The TEOF bit is used in HDLC mode to indicate that the next byte written into TBUFFER is the last byte of the frame.
TXP is used in 8-bit, stuff parity asynchronous mode to indicate the parity bit. Also, the TXHF status bit (01h:2) indicates
when the TXFIFO is half full.
When the TXFIFO is disabled (FIFOEN = 0), the TXFIFO is one byte in length.
Summary of Contents for RC336DPFL
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