RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide
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2-1
2. HARDWARE INTERFACE
2.1 HARDWARE INTERFACE SIGNALS
The functional interconnect diagram in Figure 2-1 (RCV336DPFL/SP), Figure 2-2 (RCV56DPFL/SP), and Figure 2-3
(RCVDL56DPFL/SP) show the typical MDP connections in a system. In these diagrams, any point that is active low is
represented by a small circle at the signal point.
Edge triggered inputs are denoted by a small triangle (e.g., TDCLK). An active low signal is indicated by a tilde preceding the
signal name (e.g., ~RESET).
A clock intended to activate logic on its rising edge (low-to-high transition) is called active low (e.g., ~RDCLK), while a clock
intended to activate logic on its falling edge (high-to-low transition) is called active high (e.g., TDCLK). When a clock input is
associated with a small circle, the input activates on a falling edge. If no circle is shown, the input activates on a rising edge.
The pin assignments for the MDP packaged in a single 144-pin TQFP are shown in Figure 2-4 and are listed in Table 2-1.
The hardware interface signals are described in Table 2-2.
The digital interface characteristics are defined in Table 2-3.
The analog interface characteristics are defined in Table 2-4.
The power requirements are defined in Table 2-5.
The absolute maximum ratings are listed in Table 2-6.
The timing for DTE host microprocessor interface bus waveforms is shown in Table 2-7. The host bus waveforms are
illustrated in Figure 2-5.
The DTE serial interface waveforms are illustrated in Figure 2-6.
Summary of Contents for RC336DPFL
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