RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide
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Table 3-1. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Location
Default
Name/Description
RTS
08h:0
0
Request to Send. When control bit RTS is set, the MDP transmits any data on TXD
(TPDM = 0) or TBUFFER (TPDM = 1) when CTS becomes active.
In V.22 bis, V.22, V.23, V.21, and Bell 103 constant carrier and in V.34, V.32 bis, and
V.32 modes, RTS controls data transmission and DTR controls the carrier. For ease of
use, RTS can be turned ON at the same time as DTR.
In V.22 bis controlled carrier mode, RTS independently controls the carrier when DTR
is ON. When RTS is turned ON, the MDP then transmits 270 ms of scrambled 1s
before turning CTS ON.
In V.21, V.23, V.23 HDX, and Bell 103 controlled carrier modes, RTS independently
controls the carrier when DTR is ON. When RTS is turned ON, CTS is turned ON per
Table 1-3.
In V.33, V.17, V.29, V.27, and V.21 Ch 2 fax modes, RTS controls the training
sequence transmission.
The RTS bit parallels the operation of the RTS hardware control input. These inputs
are ORed by the MDP. (See descriptions of CTS and DTR bits.)
RTSDE
02h:3
0
Remote RTS Pattern Detector Enable. When control bit RTSDE is set, the remote
RTS pattern detector is enabled. RTSDE is available in synchronous and
asynchronous modes. This bit is not valid in FSK modes. (See RTSDT).
RTSDT
0Fh:1
–
Remote RTS Pattern Detected. When set, status bit RTSDT indicates that the remote
RTS signal is ON, otherwise it indicates that the remote RTS signal is OFF. This status
bit is valid only when RTSDE is set. This status bit should be initialized by the host
upon setting RTSDE. The MDP will automatically activate/de-activate the local RLSD
signal in response to a change in the remote RTS signal. Detection is available in
synchronous and asynchronous modes. This bit is not valid in FSK modes.
RXFNE
0Ch:1
-
Receiver FIFO Not Empty. When set, status bit RXFNE indicates that the receiver
FIFO contains one or more bytes of data. When reset, bit RXFNE indicates that the
receiver FIFO is empty. As long as RXFNE = 1 or RDBF = 1, there is receive data to
be read, The host may use either bit. (TPDM = 1, FIFOEN = 1)
RXHF
01h:1
0
Receiver FIFO Half Full. When set, status bit RXHF indicates that there are 8 or more
bytes in the 16-byte Receiver FIFO buffer. When reset, RXHF indicates that there are
less than 8 bytes in the Receiver FIFO buffer. (TPDM = 1)
An interrupt mask is available to allow an interrupt request to be generated when
RXHF transitions from reset to set or from set to reset (the interrupt will occur as the
FIFO fills above the half-full point and as the FIFO empties below the half-full point)
(see Function 17 in Section 4).
RXP
01h:0
0
Received Parity Bit. This status bit is only valid when parity is enabled (PEN = 1), and
word size is set for 8 bits per character (WDSZ = 11). In this case, the parity bit
received (or ninth data bit) will be available at this location. The host must read this bit
before reading the received data buffer (RBUFFER).
RXV
11h:3
0
Receive Voice. In a tone mode or DTMF receive mode (CONF = ACh, 80h, 81h, 83h,
or 86h); control bit RXV = 1 selects receive voice ADPCM mode (CDEN = 1) or receive
voice pass-through mode (CDEN = 0); RXV = 0 disables receive voice mode.
In ADPCM receive mode (CDEN = 1), the MDP performs ADPCM coding. The coder
output is placed into the Voice Receive Buffer (VBUFR).
In receive voice pass-through mode (CDEN = 0), the host can directly access to the
A/D converter.
The host can obtain 16-bit voice samples from VBUFR at the selected sample rate
(7200 Hz default). VBUFR reflects the receive voice sample when bit RDBF is set.
(See VBUFR.)
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