RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide
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TRS
THC
THC
TRR
TDA
TDHR
TCS
RS0-RS4
~CS
~READ
D0-D7
TRS
THC
THC
TWW
TWDS
TWDH
TCS
RS0-RS4
~CS
~WRITE
D0-D7
a. Host Bus Read
b. Host Bus Write
* A minimum delay of 3 times the YCLK cycle time is required from the rising edge of
~WRITE to the falling edge of the next selected ~READ or ~WRITE. YCLK = crystal frequency/2.
A minimum delay of 20 ns is required from the rising edge of ~READ to the falling edge
of the next selected ~READ or ~WRITE.
1026F2-7 PIF WF
Figure 2-5. Host Bus Interface Waveforms
Summary of Contents for RC336DPFL
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