C - 13
2.00
Feb 07, 2011
539
25.2.5 I2C0 Clock Control Register (S20):
• Changed the last lines of the explanations of bits CCR4 to CCR0 and FASTMODE.
• Added the slave address content when the MSLAD bit in the S4D0 register is 0 to Table 25.5.
546
25.2.8 I2C0 Control Register 2 (S4D0):
• Changed the MSLAD bit name from "Slave address compare bit".
• Added ”Rewrite this bit when the TOE bit is 0.” to the TOSEL bit explanation.
548
25.2.9 I2C0 Status Register 0 (S10):
• Rewrote the LRB bit explanation.
• Changed the conditions to become 1 in the AAS bit explanation.
• Changed the conditions to become 0 in the PIN bit explanation.
553
25.2.10 I2C0 Status Register 1 (S11): Added lines 5 and 6 in the AAS0 bit explanation.
555
25.3.1.2 Bit Rate and Duty Cycle: Added the descriptions about the FASTMODE bit.
563
25.3.6 Arbitration Lost: Changed “When the ALS bit in the S1D0 register is 1” to “When the ALS bit
in the S1D0 register is 0” in the eighth line from the bottom.
Consumer Electronics Control (CEC) Function
Chap. 26. Changed “Directly address” to “Direct”.
580
Table 26.1 “CEC Function Specifications (1/2)”: Changed the first bullet in the Error detection row.
584
26.2.2 CEC Function Control Register 2 (CECC2):
• Added the description below the register diagram.
• Added the explanation about the CTABTS bit.
586
26.2.3 CEC Function Control Register 3 (CECC3):
• Added the second paragraph to the explanation about bits CTXDEN and CRXDEN.
• Deleted line 2 in the previous version and added lines 5 and 6 in the CREGCLR bit explanation.
• Changed the CEOMI bit explanation.
586
Figure 26.2 Operation of Bits CREGFLG and CREGCLR: Changed the CREGFLG bit timing.
588
26.2.4 CEC Function Control Register 4 (CECC4):
• Added “Do not write while transmitting/receiving.” to the explanations for bits CRISE2 to
CRISE0, CFALL1-CFALL0, and CABTWEN.
• Changed the CABTEN bit explanation.
• Changed the CREGFLG bit explanation.
591
26.2.6 CEC Interrupt Source Select Register (CISEL): Deleted the explanation below the register
diagram.
592
26.2.8 CEC Transmit Buffer Register 2 (CCTB2): Added “The information written to this bit is
output after the next data transmission.“ to the CCTBE bit explanation.
593
26.2.9 CEC Receive Buffer Register 1 (CCRB1): Changed the RW column from “RW” to “RO”.
594
26.2.11 CEC Receive Follower Address Set Register 1 (CRADRI1), CEC Receive Follower
Address Set Register 2 (CRADRI2): Deleted the explanation between lines 1 and 2.
600
26.3.5.3 Error Determination:
• Added the subsection title.
• Changed the second bullet.
602
Figure 26.9 Low Pulse Output Timing in Receive Error: Added.
604
Figure 26.10 Reception Example: Changed the timings of bits CRFLG, CRD8FLG, IR, and CCRBE.
605
Figure 26.11 Reception Example (Change from Error Low Pulse Output Disabled to Enabled When
an Error Occurs): Changed the timings of bits CABTEN, CRFLG, and IR.
607
26.3.6.2 Arbitration Lost Detection: Added the second bullet.
608
Figure 26.15 Transmission Example: Changed the timings of the CCRBE bit.
609
Figure 26.16 Transmission Example (When NACK Received): Changed the timing of the CTD8FLG bit.
610
Figure 26.17 Transmission Example (When an Arbitration Lost Detected):
Changed the timing of the CCRBE bit.
611
Table 26.9 “CEC1 Interrupt Sources”:
Corrected typo from “CRISEL0”
to “CTISEL0”, and from “CRISEL1”
to “CTISEL1”.
613
26.5.2 VIH of the CEC pin: Added.
A/D Converter
Chap. 27. Changed “precharge” to “charge”.
615
Figure 27.1 A/D Converter Block Diagram: Changed “Initializing cycle 2 cycles” to “2 cycles”.
624
27.3.1 A/D Conversion Cycle: Added the description to line 1.
627
27.3.6 Open-Circuit Detection Assist Function: Changed the first paragraph.
REVISION HISTORY
M16C/64A Group Hardware Manual
Rev.
Date
Description
Page
Summary
Summary of Contents for M16C/60 Series
Page 853: ...M16C 64A Group R01UH0136EJ0210...
