R01UH0136EJ0210 Rev.2.10
Page 337 of 800
Jul 31, 2012
M16C/64A Group
19. Three-Phase Motor Control Timer Function
19.2.7
Timer B2 Interrupt Generation Frequency Set Counter (ICTB2)
Use the MOV instruction to set the ICTB2 register.
If the INV01 bit in the INVC0 register is 1, set the ICTB2 register when the TB2S bit in the TABSR
register is set to 0 (timer B2 counter stopped). If the INV01 bit is 0 and the TB2S bit to 1 (timer B2
counter start), do not set the ICTB2 register when timer B2 underflows.
When bits INV01 to INV00 are 11b, the first interrupt is generated when timer B2 underflows n-1 times if
a setting value in the ICTB2 counter is n. Subsequent interrupts are generated every n times timer B2
underflows.
Timer B2 Interrupt Generation Frequency Set Counter
Symbol
ICTB2
Address
030Dh
RW
Reset Value
Undefined
b7
b0
Function
Setting Range
—
No register bits. If necessary, set to 0
WO
1 to 15
When a setting value is n, timer B2 interrupt is generated
every nth count timer B2 underflow meets the condition
selected by bits INV01 to INV00 in the INVC0 register.
Summary of Contents for M16C/60 Series
Page 853: ...M16C 64A Group R01UH0136EJ0210...
