R01UH0136EJ0210 Rev.2.10
Page 773 of 800
Jul 31, 2012
M16C/64A Group
32. Usage Notes
32.13 Notes on Timer B
32.13.1 Common Notes on Multiple Modes
32.13.1.1 Register Setting
The timer is stopped after reset. Set the mode, count source, etc., using registers TBiMR, TBCS0 to
TBCS3, TBi, PCLKR, PPWFS1, and PPWFS2 before setting the TBiS bit in the TABSR or TBSR
register to 1 (count started) (i = 0 to 5).
Rewrite registers TBiMR, TBCS0 to TBCS3, PCLKR, PPWFS1, and PPWFS2 while the TBiS bit is 0
(count stopped), regardless of whether after reset or not.
32.13.2 Timer B (Timer Mode)
32.13.2.1 Reading the Timer
While counting, the counter value can be read at any time by reading the TBi register. However,
FFFFh is read while reloading. When the counter is read before it starts counting and after a value is
set in the TBi register while not counting, the set value is read.
32.13.3 Timer B (Event Counter Mode)
32.13.3.1 Reading the Timer
While counting, the counter value can be read at any time by reading the TBi register. However,
FFFFh is read while reloading. When the counter is read before it starts counting and after a value is
set in the TBi register while not counting, the set value is read.
32.13.3.2 Event
When the TCK1 bit in the TBiMR register is 1, an event occurs when an interrupt request of the
selected timer is generated. An event or trigger occurs while an interrupt is disabled because an
interrupt request signal is generated regardless of the I flag, IPL, or interrupt control registers.
When the timer selected by the TCK1 bit uses pulse-period measurement mode or pulse-width
measurement mode, an interrupt request is generated at an active edge of the measurement pulse.
Summary of Contents for M16C/60 Series
Page 853: ...M16C 64A Group R01UH0136EJ0210...
