R01UH0136EJ0210 Rev.2.10
Page 492 of 800
Jul 31, 2012
M16C/64A Group
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.3.1
Detecting Start and Stop Conditions
Start and stop conditions are detected by their respective detectors.
Whether a start or a stop condition has been detected is determined.
A start condition detect interrupt request is generated when the SDAi pin changes state from high to low
while the SCLi pin is in the high state. A stop condition detect interrupt request is generated when the
SDAi pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition detect interrupts share the interrupt control register and vector,
check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt.
To detect a start or stop condition, both the set-up and hold times require at least six cycles of the BRGi
count source as shown in Figure 23.21. To meet the condition for the Fast-mode specification, the BRGi
count source must be at least 10 MHz.
Figure 23.21 Detecting Start and Stop Conditions
23.3.3.2
Generating Start and Stop Conditions
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2, 5 to 7) to 1
(start).
A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to 1 (start).
A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to 1 (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to 1 (start).
(2) Set the STSPSEL bit in the UiSMR4 register to 1 (output).
The functions of the STSPSEL bit are shown in Table 23.19 and Figure 23.22.
Table 23.19
STSPSEL Bit Functions
Function
STSPSEL = 0
STSPSEL = 1
Output of pins SCLi and
SDAi
Output of transmit/receive clock and
data
Output of start/stop condition is
accomplished by a program using
ports (not automatically generated in
hardware)
Output of a start/stop condition
according to bits STAREQ,
RSTAREQ, and STPREQ
Start/stop condition
Interrupt request
generation timing
Detection of start/stop condition
Completion of generating start/stop
condition
Stop condition
Set-up time
≥
6 cycles
(1)
Hold time
≥
6 cycles
(1)
Start condition
i = 0 to 2, 5 to 7
Note:
1.
The number of cycles are the BRGi count source cycles.
SDAi
SCLi
Summary of Contents for M16C/60 Series
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