Renesas M16C/60 Series, User Manual

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R01UH0136EJ0210 Rev.2.10 Page 535 of 800
Jul 31, 2012
M16C/64A Group 25. Multi-master I
2
C-bus Interface
25.2 Registers Descriptions
Table 25.4 lists registers associated with multi-master I
2
C-bus interface. When the CM07 bit in the CM0
register is set to 1 (sub clock is CPU clock), registers listed in Table 25.4 should not be accessed. Set
them after the CM07 bit is set to 0 (main clock, PLL clock, or on-chip oscillator clock).
Table 25.4 Registers
Address Register Symbol Reset Value
0012h Peripheral Clock Select Register PCLKR 0000 0011b
02B0h I2C0 Data Shift Register S00 XXh
02B2h I2C0 Address Register 0 S0D0 0000 000Xb
02B3h I2C0 Control Register 0 S1D0 00h
02B4h I2C0 Clock Control Register S20 00h
02B5h I2C0 Start/Stop Condition Control Register S2D0 0001 1010b
02B6h I2C0 Control Register 1 S3D0 0011 0000b
02B7h I2C0 Control Register 2 S4D0 00h
02B8h I2C0 Status Register 0 S10 0001 000Xb
02B9h I2C0 Status Register 1 S11 XXXX X000b
02BAh I2C0 Address Register 1 S0D1 0000 000Xb
02BBh I2C0 Address Register 2 S0D2 0000 000Xb