Renesas IDT Tsi576, User Manual

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12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 329
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
24 ILL_TRANS_ERR Illegal Transfer Error
This bit is set to 1 when the following occurs:
• Received transaction has reserved tt field for all but
maintenance packets with hop count = 0
• DestinationID is unmapped (not defined in lookup table)
Once set, the bit remains set until written with logic 1 to
clear.
The setting of this bit generates a port-write and interrupt if a
the
bit ILL_TRANS_EN bit is set in the “RapidIO Port x
Control Independent Register” on page 321 .
This bit duplicates a function of bit 0 of the “RapidIO Port x
Error Detect CSR” on page 296 , but a port-write is sent
immediately when the error is detected without exceeding
the
“RapidIO Port x Error Rate Threshold CSR” on
page 308 .
This error also reported in “RapidIO Port x Error Detect
CSR” on page 296 .
R/W1C 0
25 IRQ_ERR Interrupt Error Status
Set to one if an error occurs (refer to the “Error
Management” on page 57 ). Once set, the bit remains
unchanged until all the error sources are cleared.
The setting of this bit generates an interrupt if the IRQ_EN
bit in
“RapidIO Port x Control Independent Register” on
page 321 is set.
R 0
26 MAX_
RETRY
Maximum Retry Error
Set when number of retries has reached
MAX_RETRY_THRESHOLD. An interrupt is generated if
MAX_RETRY_EN is set. A port-write request can also be
generated if enabled.
This bit is ignored if MAX_RETRY_THRESHOLD is 0x00.
This bit is cleared by writing a 1 to it, or by clearing all bits in
the
“RapidIO Port x Error Detect CSR” on page 296 .
R/W1C 0
27 OUTB_DEPTH Outbound Depth Interrupt
This value is set when Output Queue Depth Count reaches
the maximum number defined in the Output Queue Depth
Threshold field in the
“RapidIO Port x Transmitter Output
Queue Depth Threshold Register” on page 352 .
To get an interrupt in this status register, the Outbound
Depth Interrupt Enable bit in the
“RapidIO Port x Control
Independent Register” on page 321 is set to 1.
Writing a 1 to this bit clears the interrupt and clears
CONG_CNTR in the
“RapidIO Port x Transmitter Output
Queue Congestion Status Register” on page 354 .
R/W1C 0
(Continued)
Bits Name Description Type
Reset
Value