Renesas IDT Tsi576, User Manual

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13. I2C Registers > Register Descriptions 453
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
26:27 WSIZE Internal Register Write Access Size
00 = 1 byte (Reserved)
01 = 2 bytes
10 = 4 bytes – An internal register write is invoked once for
each internal register, writing all 4 bytes from the
“Externally
Visible I
2
C Internal Write Data Register” . The write is
performed when the MSB of the data register is written
(peripheral address 0x07).
11 = 8 bytes (Reserved)
All Reserved settings will result in internal writes accesses
being disabled.
R 10
28 RINC Enable Auto-Incrementing on Internal Register Reads
0 = The “Externally Visible I
2
C Internal Read Address
Register” is unchanged after reads performed to the
“Externally Visible I
2
C Internal Read Data Register”
1 = The “Externally Visible I
2
C Internal Read Address
Register” is incremented by 4 after reads performed to the
LSB of the “Externally Visible I
2
C Internal Read Data
Register” (peripheral address 0x14) so that the address
points to the next internal register address.
When auto-incrementing is on, consecutive internal
registers can be read in one I
2
C transaction without the
need to reset the peripheral address because the peripheral
address wraps from 0x17 back to 0x14. If auto-incrementing
is off, then the same internal register can be read multiple
times in a single I
2
C transaction. The latter could be useful
for polling a status register.
R 0
29 WINC Enable Auto-Incrementing on Internal Register Writes
0 = The “Externally Visible I
2
C Internal Write Address
Register” is unchanged after reads performed to the
“Externally Visible I
2
C Internal Write Data Register” .
1 = The “Externally Visible I
2
C Internal Write Address
Register” is incremented by 4 after writes performed to the
MSB of the “Externally Visible I
2
C Internal Write Data
Register” (peripheral address 0x07) so that the address
points to the next internal register address.
When auto-incrementing is on, consecutive internal
registers can be written in one I
2
C transaction with the need
to reset the peripheral address because the peripheral
address wraps from 0x07 back to 0x04. If auto-incrementing
is off, then the same internal register can be written multiple
times in a single I
2
C transaction.
R 0
30:31 Reserved Reserved R 00
(Continued)
Bits Name Description Type
Reset
Value