Renesas IDT Tsi576, User Manual

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13. I2C Registers > Register Descriptions 472
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
08 IMBW Incoming Mailbox Write Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
09 OMBR Outgoing Mailbox Read Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
10 Reserved Reserved R 0
11 SCOL Slave Collision Detect Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
12 STRTO Slave Transaction Timeout Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
13 SBTTO Slave Byte Timeout Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
14 SSCLTO Slave I2C_SCLK Low Timeout Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
15:16 Reserved Reserved R 00
17 MTD Master Transaction Done Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
18 Reserved Reserved R 0
19 BLTO Boot Load Timeout Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
20 BLERR Boot Load Error Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
21 BLSZ Boot Load Size Error Enable
0 = Event does not assert to interrupt status
1 = Event will assert in the interrupt status
R/W 1
(Continued)
Bits Name Description Type
Reset
Value