Renesas IDT Tsi576, User Manual

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3. Serial RapidIO Electrical Interface > Port Power Down 72
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
For more information about powering down ports and special requirements for powering down port 0,
see
“Port Power Down” on page 72 .
3.4.2 Changing the Clock Speed Through I
2
C
The Tsi576 can be configured to power up with ports at different link speeds by setting the “SRIO
MAC x Digital Loopback and Clock Selection Register” on page 379 by an external I
2
C master access
or by an EEPROM boot load.
The most effective way to configure the port link speed through the I
2
C register load is to leave the port
powered down at boot time through the SP{n}_PWRDN configuration pin (see “Signal Descriptions” )
and have entries in the I
2
C EEPROM to load the appropriate contents of the
SMACn_DLOOP_CLK_SEL to power up the port and set the correct port speed.
If port 0 requires a different speed from the default speed, two I
2
C EEPROM entries are necessary
because port 0 does not have a power down configuration pin. In this case, the first I
2
C EEPROM entry
for SMAC0_DLOOP_CLK_SEL must power down the port (SMAC0_DLOOP_CLK_SEL =
0xXXXXXXXC). The second I
2
C EEPROM entry can power up the port and set IO_SPEED field in
the SMAC0_DLOOP_CLK_SEL register to the correct value and power the port back up again.
3.5 Port Power Down
All of the Tsi576 RapidIO ports can be powered down to minimize power consumption when the port
is not required. However, port 0 has special power-down requirements that must be followed (see
“Special Conditions for Port 0 Power Down” on page 73 ).
When a port is powered down, some registers return 0 and all writes to these registers are ignored.
These values indicate that the RapidIO port is uninitialized. The following register types are read only
and return zero when a port is powered-down:
• RapidIO Physical Layer Registers (see “RapidIO Physical Layer Registers” )
• RapidIO Error Management Extension Registers (see “RapidIO Error Management Extension
Registers” )
• IDT-Specific RapidIO Registers (see “IDT-Specific RapidIO Registers” )
The following register types can be read and written to when a port is powered-down:
• “Serial Port Electrical Layer Registers” on page 363
Care must be taken writing this register by an I
2
C master because the port is initialized before
the I
2
C load is completed and therefore must follow the same rules as outlined in “Changing
the Clock Speed” on page 71 .
Initializing the port speed using an I
2
C EEPROM boot load must also follow the rules
outlined in “Changing the Clock Speed” on page 71 because the port is loaded with the
power-up option selection on reset release and, although the port is prevented from
initializing during the EEPROM boot load, the PLL is running.
Both the “RapidIO Port x Error and Status CSR” on page 280 and “RapidIO Serial Port x
Control CSR” on page 283 registers return 0x00000001 when read instead of 0s.