Renesas IDT Tsi576, User Manual

Page: 246 / 530

12. Serial RapidIO Registers > Register Map 246
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
SerDes Per Lane Registers
1D000 - 1DFFC Documented in the I
2
C Register Chapter
1E000-1E01C Reserved
1E020 SMAC{0,2,4,6}_PG_CTL_0 “SerDes Lane 0 Pattern Generator Control Register” on page 405
1E024-1E02C Reserved
1E030 SMAC{0,2,4,6}_PM_CTL_0 “SerDes Lane 0 Pattern Matcher Control Register” on page 409
1E034 SMAC{0,2,4,6}_FP_VAL_0 “SerDes Lane 0 Frequency and Phase Value Register” on
page 413
1E038-1E03C Reserved
1E060 SMAC{0,2,4,6}_PG_CTL_1 “SerDes Lane 1 Pattern Generator Control Register” on page 406
1E064-1E06C Reserved
1E070 SMAC{0,2,4,6}_PM_CTL_1 “SerDes Lane 1 Pattern Matcher Control Register” on page 410
1E074 SMAC{0,2,4,6}_FP_VAL_1 “SerDes Lane 1 Frequency and Phase Value Register” on
page 414
1E078-1E07C Reserved
1E0A0 SMAC{0,2,4,6}_PG_CTL_2 “SerDes Lane 2 Pattern Generator Control Register” on page 407
1E0A4-1E0AC Reserved
1E0B0 SMAC{0,2,4,6}_PM_CTL_2 “SerDes Lane 2 Pattern Matcher Control Register” on page 411
1E0B4 SMAC{0,2,4,6}_FP_VAL_2 “SerDes Lane 2 Frequency and Phase Value Register” on
page 415
1E0B8-1E0BC Reserved
1E0E0 SMAC{0,2,4,6}_PG_CTL_3 “SerDes Lane 3 Pattern Generator Control Register” on page 408
1E0E4-1E0EC Reserved
1E0F0 SMAC{0,2,4,6}_PM_CTL_3 “SerDes Lane 3 Pattern Matcher Control Register” on page 412
1E0F4 SMAC{0,2,4,6}_FP_VAL_3 “SerDes Lane 3 Frequency and Phase Value Register” on
page 416
1E0F8-1E0FC Reserved
Table 36: Register Map (Continued)
Offset Register Name See