Renesas IDT Tsi576, User Manual

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12. Serial RapidIO Registers > IDT-Specific Performance Registers 362
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.9.16 RapidIO Port x Reordering Counter Register
When a packet cannot make forward progress due to internal switching congestion, the internal
switching fabric selects packets in an order different from the order in which the packets were received.
Each time this happens, it is counted as a “reorder” event in this register.
The Input Reordering Threshold (THRESH) defines the number of times the Input Reordering Count is
incremented before an interrupt is generated, if enabled (see
“RapidIO Port x Interrupt Status Register”
on page 328 ).
Register name: SP{0..15}_REORDER_CTR
Reset value: 0x0000_FFFF
Register offset: 130A0, 131A0, 132A0, 133A0, 134A0,
135A0, 136A0, 137A0, 138A0, 139A0, 13AA0,
13BA0, 13CA0, 13DA0, 13EA0, 13FA0
Bits 0 1 2 3 4 5 6 7
00:7 CTR
8:15 CTR
16:23 THRESH
24:31 THRESH
Bits Name Description Type
Reset
Value
0:15 CTR Reorder Counter
This counter is updated every time the input queue is reordered.
This counter counts up to 0xFFFFand remains at 0xFFFF until
reset.
The counter is reset when 1 is written to the INB_RDR status bit in
the
“RapidIO Port x Interrupt Status Register” on page 328 . The
counter is enabled if the THRESH is configured to a value other
than 0.
R/W 0x0000
16:31 THRESH Input Reordering Threshold
When CTR equals THRESH, the maskable interrupt “INB_RDR” in
the
“RapidIO Port x Interrupt Status Register” on page 328 is
generated.
Setting the THRESH value to 0 disables the CTR.
R/W 0xFFFF