13. I2C Registers > Register Descriptions
440
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
2
ALRT_EN
Alert Address Enable
0 = Do not respond to read of the Alert Response Address of
0001100
1 = Respond to read of the Alert Response Address of
0001100 if any bits are set in the
.
If enabled, the slave interface will respond to the Alert
Response Address for a read transaction if the
ALERT_FLAG is set in the
Access Status Register” on page 450
. The response is to
return the SLV_ADDR field followed by a 0 to the external
master, then clear the ALERT_FLAG. If ALRT_EN is 0, then
the Alert Response address may be used as a SLV_ADDR.
If ALRT_EN is 1 and SLV_ADDR is also set to the alert
response address, then the alert response behavior will take
precedence.
R/W
0
3
SLV_EN
Slave Enable
0 = Slave is not enabled; SLV_ADDR is ignored.
1 = Slave interface is enabled; SLV_ADDR is responded to
when transaction started by external master.
When enabled, the slave interface will acknowledge
transactions to the SLV_ADDR from an external master. If
not enabled, then all transactions are NACK’d, except the
Alert Response Address read, if ALRT_EN is 1.
This bit controls access to the peripheral address space of
the Tsi576. Access to the internal register space is also
controlled by the RD_EN and WR_EN bits. If SLV_EN is 0
then internal register access is also disabled.
R/W
1
4:6
Reserved
Reserved
R
000
7
SLV_UNLK
Slave Address Unlock
0 = The LSB 2 bits of the SLV_ADDR are locked for writing
(a write will leave those bits unchanged).
1 = The LSB 2 bits of the SLV_ADDR are unlocked, and can
be changed by a write.
This bit controls a write-protect on the 2 LSBs of the
SLV_ADDR field. When 0 those bits are not writeable, which
protects the power-up latch value of those bits. To change
the bits, this SLV_UNLK bit must be written to 1 on the write
performed to this register that is changing the
SLV_ADDR[30:31] bits.
R/W
0
8:24
Reserved
Reserved
R
0x0000
(Continued)
Bits
Name
Description
Type
Reset
Value
