12. Serial RapidIO Registers > RapidIO Error Management Extension Registers
296
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.7.9
RapidIO Port x Error Detect CSR
This register indicates transmission errors that are detected by the hardware.
Each write of a non-zero value to the Port x Error Detect CSR causes the Error Rate Counter to
increment, if the corresponding error bit is enabled in the
“RapidIO Port x Error Rate Enable CSR” on
. When the threshold is reached, hardware informs the system software of the error using its
standard error reporting function. After the error has been reported, the system software can read and
clear registers as necessary to complete its error handling protocol testing.
Register name: SP{0..15}_ERR_DET
Reset value: 0x0000_0000
Register offset: 1040, 1080, 10C0, 1100, 1140, 1180, 11C0,
1200, 1240, 1280, 12C0, 1300,
1340, 1380, 13C0, 1400
Bits
0
1
2
3
4
5
6
7
00:07
IMP_SPEC
_ERR
Reserved
08:15
Reserved
CS_CRC_E
RR
CS_ILL_ID
CS_NOT_A
CC
PKT_ILL_A
CKID
PKT_CRC_
ERR
PKT_ILL_
SIZE
Reserved
16:23
Reserved
24:31
Reserved
LR_ACKID
_ILL
PROT_
ERR
Reserved
DELIN_
ERR
CS_ACK_
ILL
LINK_TO
