2. Serial RapidIO Interface > Reset Control Symbol Processing
57
Tsi576 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
2.6
Reset Control Symbol Processing
One of the functions that can be performed by control symbols is requesting that the link partner reset
itself. The Tsi576 can generate link-request/reset control symbols using the standard RapidIO registers
defined for the purpose. The Tsi576 generates four link-request/reset control symbols with only one
register access to the
“RapidIO Serial Port x Link Maintenance Request CSR” on page 275
. For more
information on reset control symbol handling, see
.
2.7
Data Integrity Checking
Data integrity checking is performed on both control symbols and packets.
2.7.1
Packet Data Integrity Checking
Packets have two locations where CRC can occur. The first location is 80 bytes into the packet while
the second location is at the end of the packet. This means that packets 80 bytes or smaller in size have
only one CRC, while packets larger than 80 bytes have two 16 bit CRC codes. With the exception of
maintenance packets, the Tsi576 does not (re)compute CRC codes for packets. The CRC code is
forwarded with the packet across the ISF, and the packet is transmitted with the same CRC code it was
received with. This ensures that packet corruption within the Tsi576 is detected.
The exception to the rule for CRC codes is the handling of maintenance packets. Maintenance packets
have a hop count field, covered by CRC, which must be changed by the Tsi576 if the packet is to be
forwarded. So, CRC is recomputed for maintenance packets for each link they traverse.
2.7.2
Control Symbol Data Integrity Checking
Control symbols have 24 bits, five of which are devoted to a CRC code. The CRC code is verified to
ensure that the control symbol was not corrupted in transmission. Additional checks are performed on a
control symbol’s fields to ensure that they are valid. If the CRC check or the control symbols fields are
invalid, the control symbol is discarded.
2.8
Error Management
The Tsi576 supports the Software Assisted Error Recovery registers as defined by the
RapidIO
Interconnect Specification (Revision 1.3)
. Refer to
“RapidIO Physical Layer Registers” on page 270
for the complete list of registers supported for Software Assisted Error Recovery.
