Phytec phyCORE-P87C591, Quick Start Instructions

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phyCORE-P87C591 QuickStart Instructions
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© PHYTEC Meßtechnik GmbH 2002 L-586e_2
Since the phyCORE-P87C591 is equipped with a software
configurable address decoder instead of simple programmable logic
device, you can configure the memory model to your needs at
runtime.
To ensure proper execution of your application, you must take the
runtime memory model into consideration when linking and locating.
This means that you must instruct the linker where to assume external
RAM for locating data segments and Flash for locating code
segments.
The standard configuration of the phyCORE-P87C591 is equipped
with 128 kByte of external RAM and 128 kByte of external Flash.
During runtime the RAM will be addressable at 0x0000 to 0xFFFF.
The user bank (bank 1, FA[18..15] = 0010b) will be addressable at
0x0000 to 0xFFFF. This default runtime memory model requires no
additional linker settings because both RAM and Flash start at
0x0000. This is also the default start address of the linkers segment
types.
Since you can not define any end address, you should always ensure
that the size of the segments fits within the available size of the
mounted memory devices. For instance all XDATA segments should
end below 0x7FFF if a 32 kByte RAM device mounted on the
phyCORE-P87C591. We recommend generation of a *.m51 map file
for your project and inspection of the memory map information within
this file.
Whenever you modify the memory model (e.g. use von Neumann
rather than Harvard memory), which leads to different start addresses
of CODE or XDATA memory, you must configure this in the linker
settings.