Phytec phyCORE-P87C591, Quick Start Instructions

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phyCORE-P87C591 QuickStart Instructions
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© PHYTEC Meßtechnik GmbH 2002 L-586e_2
4.2.2 Setting Options for Target
When setting the memory configuration, the memory layout necessary
for the monitor must be taken into consideration.
The standard 8051 controller uses a Harvard memory architecture. In
this architecture, access to CODE and XDATA memory space goes to
physically different memory devices. Normally, for access to CODE
space, a non-volatile memory is utilized, i.e. ROM or Flash. For
access to XDATA space, a RAM is used. Using this memory model
with an 8051 derivative allows access to up to 64 kByte of memory
for CODE and 64 kByte for XDATA.
When debugging with the Raisonance monitor, it is important that the
user program (CODE) can be changed during runtime (e.g. to enable
setting of breakpoints). This requires the user program to be stored in
RAM and not in Flash. In order to ensure that the user program is
running in RAM, the monitor loader automatically configures a von
Neumann memory architecture in the address range 0000H-EFFFH
after reset. Here, in contrast to the Harvard architecture, access to
CODE and XDATA space is directed towards the same physical
memory device, normally RAM. With this von Neumann memory
architecture, it is now possible to change the application program
during runtime.