Phytec phyCORE-P87C591, Quick Start Instructions

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Advanced User Information
© PHYTEC Meßtechnik GmbH 2002 L-586e_2
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5.2 Linking and Locating
The Linker must combine several relocatable object modules
contained in object files and/or libraries to generate a single absolute
object.
In addition, the linker must locate several segments of code and data
to fixed address locations within the address space in regards to the
memory types of the phyCORE-P87C591. XDATA segments always
must be located to Random Access Memory (e.g. RAM), CODE
segments should be located to non-volatile memory (e.g. Flash). The
8051
family supports a Harvard memory architecture that
distinguishes between non-volatile and randomly accessible memory
and has two physically different signals for separate fetching of data
and code.
The Raisonance tool chain distinguishes the following segment types:
•
CODE: code
•
XDATA: external data (max. 64 kByte)
•
DATA: direct addressable on-chip data (max. 128 Byte)
•
IDATA: indirect addressable on-chip data (max. 256 Byte)
•
BIT: bit-addressable on-chip data (max. 128-bits)
The segment types DATA, IDATA and BIT always reside in the
on-chip RAM of the controller.
The segment types XDATA and CODE will usually reside in external
memory devices.
To ensure proper execution of your application, it is required that all
XDATA segments are located to the external RAM of the
phyCORE-P87C591 and that all CODE segments are located to the
external Flash memory of the phyCORE-P87C591. Exceptions may
occur if you use a 8051 derivative with on-chip portions of XDATA
(e.g. internal XRAM) or CODE (e.g. internal ROM).