2002 Nov 22
17
NXP Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
handbook, full pagewidth
MBC602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
Fig.9 Acknowledge on the I
2
C-bus.
10.7
Device address
Before any data is transmitted on the I
2
C-bus, the device
which should respond is addressed first. The addressing is
always done with byte 1 transmitted after the start
procedure.
The device address can be one out of four, being set by
pin DA0 and pin DA1.
The UDA1352TS acts as a slave receiver or a slave
transmitter. Therefore, the clock signal SCL is only an
input signal. The data signal SDA is a bidirectional line.
The UDA1352TS device address is shown in Table 10.
Table 10
I
2
C-bus device address
10.8
Register address
The register addresses in the I
2
C-bus mode are the same
as in the L3-bus mode.
10.9
Write and read data
The I
2
C-bus configuration for a write and read cycle are
shown respectively in Tables 11 and 12. The write cycle is
used to write groups of two bytes to the internal registers
for the digital sound feature control and system setting.
It is also possible to read these locations for the device
status information.
DEVICE ADDRESS
R/W
A6
A5
A4
A3
A2
A1
A0
−
1
0
0
1
1
DA1
DA0
0/1
