NXP Semiconductors UDA1352TS, Datasheet

Page: 27 / 52

2002 Nov 22 27
NXP Semiconductors Preliminary specification
48 kHz IEC 60958 audio DAC UDA1352TS
12.3 Volume control left and right (write)
Table 23 Register address 10H
Table 24 Description of register bits
Table 25 Volume settings left and right channel
BIT 15 14 13 12 11 10 9 8
Symbol VCL_7 VCL_6 VCL_5 VCL_4 VCL_3 VCL_2 VCL_1 VCL_0
Default 0 0 0 0 0 0 0 0
BIT 7 6 5 4 3 2 1 0
Symbol VCR_7 VCR_6 VCR_5 VCR_4 VCR_3 VCR_2 VCR_1 VCR_0
Default 0 0 0 0 0 0 0 0
BIT SYMBOL DESCRIPTION
15 to 8 VCL_[7:0] Volume setting left channel. A 8-bit value to program the left channel volume
attenuation. The range is 0 to
−
50 dB in steps of 0.25 dB, to
−
60 dB in steps of 1 dB,
−
66 dB and
−∞
dB. Default value 0000 0000; see Table 25.
7 to 0 VCR_[7:0] Volume setting right channel. A 8-bit value to program the right channel volume
attenuation. The range is 0 to
−
50 dB in steps of 0.25 dB, to
−
60 dB in steps of 1 dB,
−
66 dB and
−∞
dB. Default value 0000 0000; see Table 25.
VCL_7 VCL_6 VCL_5 VCL_4 VCL_3 VCL_2 VCL_1 VCL_0
VOLUME (dB)
VCR_7 VCR_6 VCR_5 VCR_4 VCR_3 VCR_2 VCR_1 VCR_0
0 0 0 0 0 0 0 0 0 (default)
0 0 0 0 0 0 0 1
−
0.25
0 0 0 0 0 0 1 0
−
0.5
: : : : : : : : :
1 1 0 0 0 1 1 1
−
49.75
1 1 0 0 1 0 0 0
−
50
1 1 0 0 1 1 0 0
−
51
1 1 0 1 0 0 0 0
−
52
: : : : : : : : :
1 1 1 1 0 0 0 0
−
60
1 1 1 1 0 1 0 0
−
66
1 1 1 1 1 0 0 0
−∞
1 1 1 1 1 1 0 0
−∞
: : : : : : : : :
1 1 1 1 1 1 1 1
−∞