NXP Semiconductors UDA1352TS, Datasheet

Page: 43 / 52

2002 Nov 22 43
NXP Semiconductors Preliminary specification
48 kHz IEC 60958 audio DAC UDA1352TS
16 TIMING CHARACTERISTICS
V
DDD
= V
DDA
= 2.4 to 3.6 V; T
amb
=
−
40 to +85
°
C; R
L
= 5 k
Ω
; all voltages measured with respect to ground; unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Device reset
t
rst
reset active time
−
250
− μ
s
PLL lock time
t
lock
time-to-lock f
s
= 32.0 kHz
−
85.0
−
ms
f
s
= 44.1 kHz
−
63.0
−
ms
f
s
= 48.0 kHz
−
60.0
−
ms
L3-bus microcontroller interface; see Figs 15 and 16
T
cy(CLK)(L3)
L3CLOCK cycle time 500
− −
ns
t
CLK(L3)H
L3CLOCK HIGH time 250
− −
ns
t
CLK(L3)L
L3CLOCK LOW time 250
− −
ns
t
su(L3)A
L3MODE set-up time in address mode 190
− −
ns
t
h(L3)A
L3MODE hold time in address mode 190
− −
ns
t
su(L3)D
L3MODE set-up time in data transfer mode 190
− −
ns
t
h(L3)D
L3MODE hold time in data transfer mode 190
− −
ns
t
(stp)(L3)
L3MODE stop time in data transfer mode 190
− −
ns
t
su(L3)DA
L3DATA set-up time in address and data
transfer mode 190
− −
ns
t
h(L3)DA
L3DATA hold time in address and data
transfer mode 30
− −
ns
t
d(L3)R
L3DATA delay time in data transfer mode 0
−
50 ns
t
dis(L3)R
L3DATA disable time for read data 0
−
50 ns
I
2
C-bus microcontroller interface; see Fig 17
f
SCL
SCL clock frequency 0
−
400 kHz
t
LOW
SCL LOW time 1.3
− − μ
s
t
HIGH
SCL HIGH time 0.6
− − μ
s
t
r
rise time SDA and SCL note 1 20 + 0.1C
b
−
300 ns
t
f
fall time SDA and SCL note 1 20 + 0.1C
b
−
300 ns
t
HD;STA
hold time start condition 0.6
− − μ
s
t
SU;STA
set-up time START condition 0.6
− − μ
s
t
SU;STO
set-up time STOP condition 0.6
− − μ
s
t
BUF
bus free time between a STOP and START
condition 1.3
− − μ
s