2002 Nov 22
23
NXP Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
11.3.3
M
INIMUM
BURST
SPACING
In order to be able to detect the start of a data burst, it is
prescribed to have a data-burst which does not exceed
4096 frames. After 4096 frames there must be a
synchronization sequence containing 2 frames of
complete zero data (being 4 times 16 bits) followed by the
preamble burst Pa and Pb. In this way a comparison with
a sync code of 96 bits can detect the start of a new
burst-payload including the Pc and Pd preambles
containing additional stream information.
11.4
Timing characteristics
11.4.1
F
REQUENCY
REQUIREMENTS
The SPDIF specification IEC 60958 supports three levels
of clock accuracy, being:
•
Level I, high accuracy: tolerance of transmitting
sampling frequency shall be within 50
×
10
−
6
•
Level II, normal accuracy: all receivers should receive a
signal of 1000
×
10
−
6
of nominal sampling frequency
•
Level III, variable pitch shifted clock mode: a deviation of
12.5% of the nominal sampling frequency is possible.
11.4.2
R
ISE
AND
FALL
TIMES
Rise and fall times (see Fig.14) are defined as:
Rise time =
Fall time =
Rise and fall times should be in the range:
•
0% to 20% when the data bit is a logic 1
•
0% to 10% when the data bits are two succeeding logic
zeros.
11.4.3
D
UTY
CYCLE
The duty cycle (see Fig.14) is defined as:
Duty cycle =
The duty cycle should be in the range:
•
40% to 60% when the data bit is a logic 1
•
45% to 55% when the data bits are two succeeding logic
zeros.
t
r
t
L
t
H
+
(
)
--------------------
100%
×
t
f
t
L
t
H
+
(
)
--------------------
100%
×
t
H
t
L
t
H
+
(
)
--------------------
100%
×
handbook, halfpage
90%
tH
50%
10%
MGU612
tr
tf
tL
Fig.14 Rise and fall times.
