2002 Nov 22
10
NXP Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
8.4.5
F
ILTER
STREAM
DAC
The Filter Stream DAC (FSDAC) is a semi-digital
reconstruction filter that converts the 1-bit data stream of
the noise shaper to an analog output voltage.
The filter coefficients are implemented as current sources
and are summed at virtual ground of the output operational
amplifier. In this way, very high signal-to-noise
performance and low clock jitter sensitivity is achieved.
A post filter is not needed due to the inherent filter function
of the DAC. On-board amplifiers convert the FSDAC
output current to an output voltage signal capable of
driving a line output.
The output voltage of the FSDAC is scaled proportionally
with the power supply voltage.
8.5
Control
The UDA1352TS can be controlled by means of static pins
(when pin SELSTATIC = HIGH), via the I
2
C-bus (when
pin SELSTATIC = LOW and pin SELIIC = HIGH) or via the
L3-bus (when pins SELSTATIC and SELIIC are LOW).
For optimum use of the features of the UDA1352TS, the
L3-bus or I
2
C-bus mode is recommended since only basic
functions are available in the static pin control mode.
It should be noted that the static pin control mode and the
L3-bus or I
2
C-bus mode are mutually exclusive.
8.5.1
S
TATIC
PIN
CONTROL
MODE
The default values for all non-pin controlled settings are
identical to the default values at start-up in the L3-bus or
I
2
C-bus mode (see Table 3).
Table 3
Pin description of static pin control mode
PIN
NAME
VALUE
FUNCTION
Mode selection pin
26
SELSTATIC
1
select static pin control mode; must be connected to V
DDD
Input pins
5
RESET
0
normal operation
1
reset
9
L3CLOCK
0
must be connected to V
SSD
10
L3MODE
0
must be connected to V
SSD
8
L3DATA
0
must be connected to V
SSD
11
MUTE
0
no mute
1
mute active
Status pins
1
PCMDET
0
non-PCM data or burst preamble detected
1
PCM data detected
16
LOCK
0
clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected
1
clock regeneration and IEC 60958 decoder locked and PCM data detected
Test pins
2
TEST1
−
must be left open-circuit
18
TEST2
0
must be connected to V
SSD
