2002 Nov 22
31
NXP Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
12.6
Polarity (write)
Table 33
Register address 14H
Table 34
Description of register bits
BIT
15
14
13
12
11
10
9
8
Symbol
DA_POL_
INV
−
−
−
−
−
−
−
Default
0
1
−
−
−
−
1
0
BIT
7
6
5
4
3
2
1
0
Symbol
−
−
−
−
−
−
−
−
Default
0
−
−
−
−
−
−
−
BIT
SYMBOL
DESCRIPTION
15
DA_POL_INV
DAC polarity control.
A 1-bit value to control the signal polarity of the DAC output
signal. If this bit is logic 0, then the DAC output is not inverted. If this bit is logic 1, then
the DAC output is inverted. Default value 0.
14
−
When writing new settings via the L3-bus or I
2
C-bus interface, this bit should always
remain at logic 1 (default value) to guarantee correct operation.
13 to 10
−
reserved
9
−
When writing new settings via the L3-bus or I
2
C-bus interface, this bit should always
remain at logic 1 (default value) to guarantee correct operation.
8 to 7
−
When writing new settings via the L3-bus or I
2
C-bus interface, these bits should always
remain at logic 0 (default value) to guarantee correct operation.
6 to 0
−
reserved
